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[amd] vega20: added preliminary BACO reset (untested)

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This commit is contained in:
Geoffrey McRae 2020-11-11 09:55:44 +11:00
parent e45a309e01
commit 255660bd5b
11 changed files with 1404 additions and 14 deletions
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1
src/amd/Makefile
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@ -8,6 +8,7 @@ vendor-reset-y += \
src/amd/navi10.o \
src/amd/amdgpu/common_baco.o \
src/amd/amdgpu/vega10_reg_init.o \
src/amd/amdgpu/vega20_reg_init.o \
src/amd/amdgpu/navi10_reg_init.o \
src/amd/amdgpu/navi12_reg_init.o \
src/amd/amdgpu/navi14_reg_init.o \

1
src/amd/amdgpu/amdgpu_device.c
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@ -28,6 +28,7 @@
#include <linux/module.h>
#include "common_defs.h"
#include "common.h"
/*

1051
src/amd/amdgpu/include/vega20_ip_offset.h Normal file
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131
src/amd/amdgpu/include/vega20_ppsmc.h Normal file
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@ -0,0 +1,131 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef VEGA20_PP_SMC_H
#define VEGA20_PP_SMC_H
#pragma pack(push, 1)
// SMU Response Codes:
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
#define PPSMC_MSG_EnableAllSmuFeatures 0x6
#define PPSMC_MSG_DisableAllSmuFeatures 0x7
#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
#define PPSMC_MSG_SetWorkloadMask 0xE
#define PPSMC_MSG_SetPptLimit 0xF
#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
#define PPSMC_MSG_SetDriverDramAddrLow 0x11
#define PPSMC_MSG_SetToolsDramAddrHigh 0x12
#define PPSMC_MSG_SetToolsDramAddrLow 0x13
#define PPSMC_MSG_TransferTableSmu2Dram 0x14
#define PPSMC_MSG_TransferTableDram2Smu 0x15
#define PPSMC_MSG_UseDefaultPPTable 0x16
#define PPSMC_MSG_UseBackupPPTable 0x17
#define PPSMC_MSG_RunBtc 0x18
#define PPSMC_MSG_RequestI2CBus 0x19
#define PPSMC_MSG_ReleaseI2CBus 0x1A
#define PPSMC_MSG_SetFloorSocVoltage 0x21
#define PPSMC_MSG_SoftReset 0x22
#define PPSMC_MSG_StartBacoMonitor 0x23
#define PPSMC_MSG_CancelBacoMonitor 0x24
#define PPSMC_MSG_EnterBaco 0x25
#define PPSMC_MSG_SetSoftMinByFreq 0x26
#define PPSMC_MSG_SetSoftMaxByFreq 0x27
#define PPSMC_MSG_SetHardMinByFreq 0x28
#define PPSMC_MSG_SetHardMaxByFreq 0x29
#define PPSMC_MSG_GetMinDpmFreq 0x2A
#define PPSMC_MSG_GetMaxDpmFreq 0x2B
#define PPSMC_MSG_GetDpmFreqByIndex 0x2C
#define PPSMC_MSG_GetDpmClockFreq 0x2D
#define PPSMC_MSG_GetSsVoltageByDpm 0x2E
#define PPSMC_MSG_SetMemoryChannelConfig 0x2F
#define PPSMC_MSG_SetGeminiMode 0x30
#define PPSMC_MSG_SetGeminiApertureHigh 0x31
#define PPSMC_MSG_SetGeminiApertureLow 0x32
#define PPSMC_MSG_SetMinLinkDpmByIndex 0x33
#define PPSMC_MSG_OverridePcieParameters 0x34
#define PPSMC_MSG_OverDriveSetPercentage 0x35
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x36
#define PPSMC_MSG_ReenableAcDcInterrupt 0x37
#define PPSMC_MSG_NotifyPowerSource 0x38
#define PPSMC_MSG_SetUclkFastSwitch 0x39
#define PPSMC_MSG_SetUclkDownHyst 0x3A
//#define PPSMC_MSG_GfxDeviceDriverReset 0x3B
#define PPSMC_MSG_GetCurrentRpm 0x3C
#define PPSMC_MSG_SetVideoFps 0x3D
#define PPSMC_MSG_SetTjMax 0x3E
#define PPSMC_MSG_SetFanTemperatureTarget 0x3F
#define PPSMC_MSG_PrepareMp1ForUnload 0x40
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x41
#define PPSMC_MSG_DramLogSetDramAddrLow 0x42
#define PPSMC_MSG_DramLogSetDramSize 0x43
#define PPSMC_MSG_SetFanMaxRpm 0x44
#define PPSMC_MSG_SetFanMinPwm 0x45
#define PPSMC_MSG_ConfigureGfxDidt 0x46
#define PPSMC_MSG_NumOfDisplays 0x47
#define PPSMC_MSG_RemoveMargins 0x48
#define PPSMC_MSG_ReadSerialNumTop32 0x49
#define PPSMC_MSG_ReadSerialNumBottom32 0x4A
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
#define PPSMC_MSG_WaflTest 0x4D
#define PPSMC_MSG_SetFclkGfxClkRatio 0x4E
// Unused ID 0x4F to 0x50
#define PPSMC_MSG_AllowGfxOff 0x51
#define PPSMC_MSG_DisallowGfxOff 0x52
#define PPSMC_MSG_GetPptLimit 0x53
#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x54
#define PPSMC_MSG_GetDebugData 0x55
#define PPSMC_MSG_SetXgmiMode 0x56
#define PPSMC_MSG_RunAfllBtc 0x57
#define PPSMC_MSG_ExitBaco 0x58
#define PPSMC_MSG_PrepareMp1ForReset 0x59
#define PPSMC_MSG_PrepareMp1ForShutdown 0x5A
#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D
#define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F
#define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60
#define PPSMC_MSG_DFCstateControl 0x63
#define PPSMC_Message_Count 0x64
typedef uint32_t PPSMC_Result;
typedef uint32_t PPSMC_Msg;
#pragma pack(pop)
#endif

56
src/amd/amdgpu/vega20_reg_init.c Normal file
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@ -0,0 +1,56 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "soc15.h"
#include "soc15_common.h"
#include "vega20_ip_offset.h"
#include "common.h"
int vega20_reg_base_init(struct amd_fake_dev *adev)
{
/* HW has more IP blocks, only initialized the blocke beend by our driver */
uint32_t i;
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
}
return 0;
}

1
src/amd/common.c
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@ -24,6 +24,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include "vendor-reset-dev.h"
#include "soc15_common.h"
#include "soc15.h"
#include "common_defs.h"
#include "common.h"
#include "compat.h"

10
src/amd/common.h
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@ -23,16 +23,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include <linux/kernel.h>
#include "vendor-reset-dev.h"
/* from amdgpu_discovery.c */
#ifndef mmMM_INDEX
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define HW_ID_MAX 300
#endif
/* end from amdgpu_discovery.c */
#define RREG32(reg) \
({ \
u32 __out; \

33
src/amd/common_defs.h Normal file
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@ -0,0 +1,33 @@
/*
Vendor Reset - Vendor Specific Reset
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free Software
Foundation; either version 2 of the License, or (at your option) any later
version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __VENDOR_RESET_COMMON_DEFS_H__
#define __VENDOR_RESET_COMMON_DEFS_H__
/* from amdgpu_discovery.c */
#ifndef mmMM_INDEX
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define HW_ID_MAX 300
#endif
/* end from amdgpu_discovery.c */
#endif

1
src/amd/firmware.c
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@ -21,6 +21,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include "atom.h"
#include "amdgpu_atomfirmware.h"
#include "compat.h"
#include "common_defs.h"
#include "common.h"
#include "firmware.h"

1
src/amd/navi10.c
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@ -22,6 +22,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include "vendor-reset-dev.h"
#include "amd.h"
#include "common_defs.h"
#include "common.h"
#include "firmware.h"
#include "amdgpu_discovery.h"

128
src/amd/vega20.c
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@ -18,12 +18,136 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include "vendor-reset-dev.h"
#include <linux/delay.h>
#include "nbio_7_4_offset.h"
#include "nbio_7_4_sh_mask.h"
#include "thm_11_0_2_offset.h"
#include "thm_11_0_2_sh_mask.h"
#include "mp_9_0_offset.h"
#include "mp_9_0_sh_mask.h"
#include "common.h"
#include "soc15.h"
#include "soc15_common.h"
#include "common_baco.h"
#include "vega20_ppsmc.h"
static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
{
{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
};
extern int vega20_reg_base_init(struct amd_fake_dev *adev);
static int vega20_baco_get_state(struct amd_fake_dev *adev, enum BACO_STATE *state)
{
uint32_t reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
static int vega20_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state)
{
enum BACO_STATE cur_state;
uint32_t data;
vega20_baco_get_state(adev, &cur_state);
if (cur_state == state)
return 0;
if (state == BACO_STATE_IN)
{
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
data |= 0x80000000;
WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
if (smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_EnterBaco, 0, NULL))
return -EINVAL;
}
else
{
if (smum_send_msg_to_smc(adev, PPSMC_MSG_ExitBaco, NULL))
return -EINVAL;
if (!soc15_baco_program_registers(adev, clean_baco_tbl,
ARRAY_SIZE(clean_baco_tbl)))
return -EINVAL;
}
return 0;
}
static int amd_vega20_reset(struct vendor_reset_dev *dev)
{
return 0;
struct amd_vendor_private *priv = amd_private(dev);
struct amd_fake_dev *adev;
int ret = 0, timeout;
u32 sol;
enum BACO_STATE baco_state;
adev = &priv->adev;
ret = amd_fake_dev_init(adev, dev);
if (ret)
return ret;
ret = vega20_reg_base_init(&priv->adev);
if (ret)
goto free_adev;
/* it's important we wait for the SOC to be ready */
for (timeout = 100000; timeout; --timeout)
{
sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol != 0xFFFFFFFF && sol != 0)
break;
udelay(1);
}
vega20_baco_get_state(adev, &baco_state);
if (sol == ~1L && baco_state != BACO_STATE_IN)
{
pci_warn(dev->pdev, "vega20: Timed out waiting for SOL to be valid\n");
ret = -EINVAL;
goto free_adev;
}
/* if there's no sign of life we usually can't reset */
if (!sol)
goto free_adev;
ret = vega20_baco_set_state(adev, BACO_STATE_IN);
if (ret)
{
pci_warn(dev->pdev, "vega20: enter BACO failed\n");
goto free_adev;
}
ret = vega20_baco_set_state(adev, BACO_STATE_OUT);
if (ret)
{
pci_warn(dev->pdev, "vega20: exit BACO failed\n");
goto free_adev;
}
pci_info(dev->pdev, "vega20: BACO reset successful\n");
free_adev:
amd_fake_dev_fini(adev);
return ret;
}
const struct vendor_reset_ops amd_vega20_ops =
{
.reset = amd_vega20_reset
.pre_reset = amd_common_pre_reset,
.reset = amd_vega20_reset,
.post_reset = amd_common_post_reset,
};