mirror of
https://github.com/gnif/vendor-reset.git
synced 2025-12-27 06:19:29 +01:00
[amd] vega20: added preliminary BACO reset (untested)
This commit is contained in:
Geoffrey McRae
parent
e45a309e01
commit
255660bd5b
@ -8,6 +8,7 @@ vendor-reset-y += \
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src/amd/navi10.o \
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src/amd/amdgpu/common_baco.o \
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src/amd/amdgpu/vega10_reg_init.o \
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src/amd/amdgpu/vega20_reg_init.o \
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src/amd/amdgpu/navi10_reg_init.o \
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src/amd/amdgpu/navi12_reg_init.o \
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src/amd/amdgpu/navi14_reg_init.o \
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@ -28,6 +28,7 @@
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#include <linux/module.h>
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#include "common_defs.h"
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#include "common.h"
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/*
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1051
src/amd/amdgpu/include/vega20_ip_offset.h
Normal file
1051
src/amd/amdgpu/include/vega20_ip_offset.h
Normal file
File diff suppressed because it is too large
Load Diff
131
src/amd/amdgpu/include/vega20_ppsmc.h
Normal file
131
src/amd/amdgpu/include/vega20_ppsmc.h
Normal file
@ -0,0 +1,131 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef VEGA20_PP_SMC_H
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#define VEGA20_PP_SMC_H
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#pragma pack(push, 1)
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// SMU Response Codes:
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#define PPSMC_Result_OK 0x1
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#define PPSMC_Result_Failed 0xFF
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#define PPSMC_Result_UnknownCmd 0xFE
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#define PPSMC_Result_CmdRejectedPrereq 0xFD
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#define PPSMC_Result_CmdRejectedBusy 0xFC
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// Message Definitions:
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#define PPSMC_MSG_TestMessage 0x1
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#define PPSMC_MSG_GetSmuVersion 0x2
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#define PPSMC_MSG_GetDriverIfVersion 0x3
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#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
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#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
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#define PPSMC_MSG_EnableAllSmuFeatures 0x6
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#define PPSMC_MSG_DisableAllSmuFeatures 0x7
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#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
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#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
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#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
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#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
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#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
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#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
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#define PPSMC_MSG_SetWorkloadMask 0xE
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#define PPSMC_MSG_SetPptLimit 0xF
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#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
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#define PPSMC_MSG_SetDriverDramAddrLow 0x11
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#define PPSMC_MSG_SetToolsDramAddrHigh 0x12
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#define PPSMC_MSG_SetToolsDramAddrLow 0x13
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#define PPSMC_MSG_TransferTableSmu2Dram 0x14
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#define PPSMC_MSG_TransferTableDram2Smu 0x15
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#define PPSMC_MSG_UseDefaultPPTable 0x16
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#define PPSMC_MSG_UseBackupPPTable 0x17
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#define PPSMC_MSG_RunBtc 0x18
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#define PPSMC_MSG_RequestI2CBus 0x19
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#define PPSMC_MSG_ReleaseI2CBus 0x1A
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#define PPSMC_MSG_SetFloorSocVoltage 0x21
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#define PPSMC_MSG_SoftReset 0x22
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#define PPSMC_MSG_StartBacoMonitor 0x23
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#define PPSMC_MSG_CancelBacoMonitor 0x24
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#define PPSMC_MSG_EnterBaco 0x25
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#define PPSMC_MSG_SetSoftMinByFreq 0x26
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#define PPSMC_MSG_SetSoftMaxByFreq 0x27
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#define PPSMC_MSG_SetHardMinByFreq 0x28
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#define PPSMC_MSG_SetHardMaxByFreq 0x29
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#define PPSMC_MSG_GetMinDpmFreq 0x2A
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#define PPSMC_MSG_GetMaxDpmFreq 0x2B
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#define PPSMC_MSG_GetDpmFreqByIndex 0x2C
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#define PPSMC_MSG_GetDpmClockFreq 0x2D
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#define PPSMC_MSG_GetSsVoltageByDpm 0x2E
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#define PPSMC_MSG_SetMemoryChannelConfig 0x2F
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#define PPSMC_MSG_SetGeminiMode 0x30
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#define PPSMC_MSG_SetGeminiApertureHigh 0x31
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#define PPSMC_MSG_SetGeminiApertureLow 0x32
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#define PPSMC_MSG_SetMinLinkDpmByIndex 0x33
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#define PPSMC_MSG_OverridePcieParameters 0x34
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#define PPSMC_MSG_OverDriveSetPercentage 0x35
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#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x36
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#define PPSMC_MSG_ReenableAcDcInterrupt 0x37
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#define PPSMC_MSG_NotifyPowerSource 0x38
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#define PPSMC_MSG_SetUclkFastSwitch 0x39
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#define PPSMC_MSG_SetUclkDownHyst 0x3A
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//#define PPSMC_MSG_GfxDeviceDriverReset 0x3B
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#define PPSMC_MSG_GetCurrentRpm 0x3C
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#define PPSMC_MSG_SetVideoFps 0x3D
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#define PPSMC_MSG_SetTjMax 0x3E
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#define PPSMC_MSG_SetFanTemperatureTarget 0x3F
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#define PPSMC_MSG_PrepareMp1ForUnload 0x40
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#define PPSMC_MSG_DramLogSetDramAddrHigh 0x41
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#define PPSMC_MSG_DramLogSetDramAddrLow 0x42
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#define PPSMC_MSG_DramLogSetDramSize 0x43
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#define PPSMC_MSG_SetFanMaxRpm 0x44
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#define PPSMC_MSG_SetFanMinPwm 0x45
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#define PPSMC_MSG_ConfigureGfxDidt 0x46
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#define PPSMC_MSG_NumOfDisplays 0x47
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#define PPSMC_MSG_RemoveMargins 0x48
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#define PPSMC_MSG_ReadSerialNumTop32 0x49
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#define PPSMC_MSG_ReadSerialNumBottom32 0x4A
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#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
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#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
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#define PPSMC_MSG_WaflTest 0x4D
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#define PPSMC_MSG_SetFclkGfxClkRatio 0x4E
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// Unused ID 0x4F to 0x50
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#define PPSMC_MSG_AllowGfxOff 0x51
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#define PPSMC_MSG_DisallowGfxOff 0x52
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#define PPSMC_MSG_GetPptLimit 0x53
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#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x54
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#define PPSMC_MSG_GetDebugData 0x55
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#define PPSMC_MSG_SetXgmiMode 0x56
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#define PPSMC_MSG_RunAfllBtc 0x57
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#define PPSMC_MSG_ExitBaco 0x58
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#define PPSMC_MSG_PrepareMp1ForReset 0x59
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#define PPSMC_MSG_PrepareMp1ForShutdown 0x5A
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#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D
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#define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F
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#define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60
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#define PPSMC_MSG_DFCstateControl 0x63
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#define PPSMC_Message_Count 0x64
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typedef uint32_t PPSMC_Result;
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typedef uint32_t PPSMC_Msg;
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#pragma pack(pop)
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#endif
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56
src/amd/amdgpu/vega20_reg_init.c
Normal file
56
src/amd/amdgpu/vega20_reg_init.c
Normal file
@ -0,0 +1,56 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "soc15.h"
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#include "soc15_common.h"
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#include "vega20_ip_offset.h"
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#include "common.h"
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int vega20_reg_base_init(struct amd_fake_dev *adev)
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{
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/* HW has more IP blocks, only initialized the blocke beend by our driver */
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uint32_t i;
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for (i = 0 ; i < MAX_INSTANCE ; ++i) {
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adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
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adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
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adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
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adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
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adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
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adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
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adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
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adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
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adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
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adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
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adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
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adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
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adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
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adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
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adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
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adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
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}
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return 0;
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}
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@ -24,6 +24,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "vendor-reset-dev.h"
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#include "soc15_common.h"
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#include "soc15.h"
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#include "common_defs.h"
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#include "common.h"
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#include "compat.h"
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@ -23,16 +23,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include <linux/kernel.h>
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#include "vendor-reset-dev.h"
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/* from amdgpu_discovery.c */
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#ifndef mmMM_INDEX
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#define mmRCC_CONFIG_MEMSIZE 0xde3
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#define mmMM_INDEX 0x0
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#define mmMM_INDEX_HI 0x6
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#define mmMM_DATA 0x1
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#define HW_ID_MAX 300
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#endif
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/* end from amdgpu_discovery.c */
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#define RREG32(reg) \
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({ \
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u32 __out; \
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33
src/amd/common_defs.h
Normal file
33
src/amd/common_defs.h
Normal file
@ -0,0 +1,33 @@
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/*
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Vendor Reset - Vendor Specific Reset
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Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
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Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any later
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version.
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This program is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __VENDOR_RESET_COMMON_DEFS_H__
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#define __VENDOR_RESET_COMMON_DEFS_H__
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/* from amdgpu_discovery.c */
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#ifndef mmMM_INDEX
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#define mmRCC_CONFIG_MEMSIZE 0xde3
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#define mmMM_INDEX 0x0
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#define mmMM_INDEX_HI 0x6
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#define mmMM_DATA 0x1
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#define HW_ID_MAX 300
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#endif
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/* end from amdgpu_discovery.c */
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#endif
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@ -21,6 +21,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "atom.h"
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#include "amdgpu_atomfirmware.h"
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#include "compat.h"
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#include "common_defs.h"
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#include "common.h"
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#include "firmware.h"
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@ -22,6 +22,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "vendor-reset-dev.h"
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#include "amd.h"
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#include "common_defs.h"
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#include "common.h"
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#include "firmware.h"
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#include "amdgpu_discovery.h"
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128
src/amd/vega20.c
128
src/amd/vega20.c
@ -18,12 +18,136 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "vendor-reset-dev.h"
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#include <linux/delay.h>
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#include "nbio_7_4_offset.h"
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#include "nbio_7_4_sh_mask.h"
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#include "thm_11_0_2_offset.h"
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#include "thm_11_0_2_sh_mask.h"
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#include "mp_9_0_offset.h"
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#include "mp_9_0_sh_mask.h"
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#include "common.h"
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#include "soc15.h"
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#include "soc15_common.h"
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#include "common_baco.h"
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#include "vega20_ppsmc.h"
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static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
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{
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{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
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{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
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};
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extern int vega20_reg_base_init(struct amd_fake_dev *adev);
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static int vega20_baco_get_state(struct amd_fake_dev *adev, enum BACO_STATE *state)
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{
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uint32_t reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
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if (reg & BACO_CNTL__BACO_MODE_MASK)
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/* gfx has already entered BACO state */
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*state = BACO_STATE_IN;
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else
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*state = BACO_STATE_OUT;
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return 0;
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}
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static int vega20_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state)
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{
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enum BACO_STATE cur_state;
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uint32_t data;
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vega20_baco_get_state(adev, &cur_state);
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if (cur_state == state)
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return 0;
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if (state == BACO_STATE_IN)
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{
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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data |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
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if (smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_EnterBaco, 0, NULL))
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return -EINVAL;
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}
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else
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{
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if (smum_send_msg_to_smc(adev, PPSMC_MSG_ExitBaco, NULL))
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return -EINVAL;
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if (!soc15_baco_program_registers(adev, clean_baco_tbl,
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ARRAY_SIZE(clean_baco_tbl)))
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return -EINVAL;
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}
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return 0;
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}
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static int amd_vega20_reset(struct vendor_reset_dev *dev)
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{
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return 0;
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev;
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int ret = 0, timeout;
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u32 sol;
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enum BACO_STATE baco_state;
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adev = &priv->adev;
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ret = amd_fake_dev_init(adev, dev);
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if (ret)
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return ret;
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ret = vega20_reg_base_init(&priv->adev);
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if (ret)
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goto free_adev;
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|
||||
/* it's important we wait for the SOC to be ready */
|
||||
for (timeout = 100000; timeout; --timeout)
|
||||
{
|
||||
sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
|
||||
if (sol != 0xFFFFFFFF && sol != 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
vega20_baco_get_state(adev, &baco_state);
|
||||
if (sol == ~1L && baco_state != BACO_STATE_IN)
|
||||
{
|
||||
pci_warn(dev->pdev, "vega20: Timed out waiting for SOL to be valid\n");
|
||||
ret = -EINVAL;
|
||||
goto free_adev;
|
||||
}
|
||||
|
||||
/* if there's no sign of life we usually can't reset */
|
||||
if (!sol)
|
||||
goto free_adev;
|
||||
|
||||
ret = vega20_baco_set_state(adev, BACO_STATE_IN);
|
||||
if (ret)
|
||||
{
|
||||
pci_warn(dev->pdev, "vega20: enter BACO failed\n");
|
||||
goto free_adev;
|
||||
}
|
||||
|
||||
ret = vega20_baco_set_state(adev, BACO_STATE_OUT);
|
||||
if (ret)
|
||||
{
|
||||
pci_warn(dev->pdev, "vega20: exit BACO failed\n");
|
||||
goto free_adev;
|
||||
}
|
||||
|
||||
pci_info(dev->pdev, "vega20: BACO reset successful\n");
|
||||
|
||||
free_adev:
|
||||
amd_fake_dev_fini(adev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct vendor_reset_ops amd_vega20_ops =
|
||||
{
|
||||
.reset = amd_vega20_reset
|
||||
.pre_reset = amd_common_pre_reset,
|
||||
.reset = amd_vega20_reset,
|
||||
.post_reset = amd_common_post_reset,
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user