Makussu/vendor-reset
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[core] added vr_* logging macros and refactored to use them

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This commit is contained in:
Geoffrey McRae
2020-11-14 13:24:26 +11:00
parent 78363b9353
commit 6b943a0376
11 changed files with 160 additions and 153 deletions
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2
src/amd/common.c
View File

@@ -68,7 +68,7 @@ int amd_common_pre_reset(struct vendor_reset_dev *dev)
}
}
if (!priv->rio_mem)
pci_warn(pdev, "Could not map I/O\n");
vr_warn(dev, "Could not map I/O\n");
pci_set_power_state(pdev, PCI_D0);
pci_clear_master(pdev);

3
src/amd/compat.c
View File

@@ -25,6 +25,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
int amd_fake_dev_init(struct amd_fake_dev *adev, struct vendor_reset_dev *vdev)
{
adev->vdev = vdev;
adev->pdev = vdev->pdev;
adev->dev = &vdev->pdev->dev;
@@ -44,4 +45,4 @@ void amd_fake_dev_fini(struct amd_fake_dev *adev)
kfree(adev->bios);
adev->bios = NULL;
}
}
}

3
src/amd/compat.h
View File

@@ -78,6 +78,7 @@ struct amd_fake_dev
struct card_info card_info;
struct atom_context *atom_context;
struct vendor_reset_dev *vdev;
struct pci_dev *pdev;
struct device *dev;
};
@@ -86,4 +87,4 @@ struct vendor_reset_dev;
int amd_fake_dev_init(struct amd_fake_dev *adev, struct vendor_reset_dev *vdev);
void amd_fake_dev_fini(struct amd_fake_dev *adev);
#endif
#endif

65
src/amd/navi10.c
View File

@@ -33,11 +33,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include "psp_gfx_if.h"
#include "nv.h"
static const char * log_prefix;
#define nv_info(fmt, arg...) pci_info(dev->pdev, "%s: " fmt, log_prefix, ##arg)
#define nv_warn(fmt, arg...) pci_warn(dev->pdev, "%s: " fmt, log_prefix, ##arg)
#define nv_err(fmt, arg...) pci_err(dev->pdev, "%s: " fmt, log_prefix, ##arg)
extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
static int amd_navi10_reset(struct vendor_reset_dev *dev)
@@ -52,20 +47,10 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
if (ret)
return ret;
switch (dev->info)
{
case AMD_NAVI10: log_prefix = "navi10"; break;
case AMD_NAVI12: log_prefix = "navi12"; break;
case AMD_NAVI14: log_prefix = "navi14"; break;
default:
pci_err(dev->pdev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device);
return -ENOTSUPP;
}
ret = amdgpu_discovery_reg_base_init(adev);
if (ret < 0)
{
nv_info("amdgpu_discovery_reg_base_init failed, using legacy method\n");
vr_info(dev, "amdgpu_discovery_reg_base_init failed, using legacy method\n");
switch (dev->info)
{
case AMD_NAVI10:
@@ -78,14 +63,14 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
navi14_reg_base_init(adev);
break;
default:
/* should never happen */
vr_err(dev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device);
return -ENOTSUPP;
}
}
if (!amdgpu_get_bios(adev))
{
nv_err("amdgpu_get_bios failed: %d\n", ret);
vr_err(dev, "amdgpu_get_bios failed: %d\n", ret);
ret = -ENOTSUPP;
goto free_adev;
}
@@ -93,7 +78,7 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
ret = atom_bios_init(adev);
if (ret)
{
nv_err("atom_bios_init failed: %d\n", ret);
vr_err(dev, "atom_bios_init failed: %d\n", ret);
goto free_adev;
}
@@ -108,11 +93,11 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
if (sol == ~1L)
{
nv_warn("Timed out waiting for SOL to be valid\n");
vr_warn(dev, "Timed out waiting for SOL to be valid\n");
/* continuing anyway because sometimes it can still be reset from here */
}
nv_info("bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
vr_info(dev, "bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
/* collect some info for logging for now */
smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
@@ -121,7 +106,7 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
psp_bl_ready = !!(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L);
nv_info("SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
vr_info(dev, "SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
smu_resp, sol, mp1_intr ? "yes" : "no",
psp_bl_ready ? "yes" : "no");
@@ -130,7 +115,7 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
goto free_adev;
/* this tells the drivers nvram is lost and everything needs to be reset */
nv_info("Clearing scratch regs 6 and 7\n");
vr_info(dev, "Clearing scratch regs 6 and 7\n");
WREG32(adev->bios_scratch_reg_offset + 6, 0);
WREG32(adev->bios_scratch_reg_offset + 7, 0);
@@ -141,13 +126,13 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
*/
if (smu_resp != 0x01 && mp1_intr)
{
nv_info("MP1 reset\n");
vr_info(dev, "MP1 reset\n");
WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
1 & MP1_SMN_PUB_CTRL__RESET_MASK);
WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
nv_info("wait for MP1\n");
vr_info(dev, "wait for MP1\n");
for (timeout = 100000; timeout; --timeout)
{
tmp = RREG32_PCIE(MP1_Public |
@@ -163,12 +148,12 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
!((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT))
{
nv_warn("timed out waiting for MP1 reset\n");
vr_warn(dev, "timed out waiting for MP1 reset\n");
}
smu_wait(adev);
smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
nv_info("SMU resp reg: %x\n", tmp);
vr_info(dev, "SMU resp reg: %x\n", tmp);
}
/*
@@ -181,14 +166,14 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
smu_wait(adev);
/* disallowgfx_off or something */
nv_info("gfx off\n");
vr_info(dev, "gfx off\n");
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A);
smu_wait(adev);
/* stop SMC */
nv_info("Prep Reset\n");
vr_info(dev, "Prep Reset\n");
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
/* PPSMC_MSG_PrepareMp1ForReset */
@@ -196,35 +181,35 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
smu_wait(adev);
}
nv_info("begin psp mode 1 reset\n");
vr_info(dev, "begin psp mode 1 reset\n");
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
pci_save_state(dev->pdev);
/* check validity of PSP before reset */
nv_info("PSP wait\n");
vr_info(dev, "PSP wait\n");
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
if (tmp)
nv_warn("timed out waiting for PSP to reach valid state, but continuing anyway\n");
vr_warn(dev, "timed out waiting for PSP to reach valid state, but continuing anyway\n");
/* reset command */
nv_info("do mode1 reset\n");
vr_info(dev, "do mode1 reset\n");
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
msleep(500);
/* wait for ACK */
nv_info("PSP wait\n");
vr_info(dev, "PSP wait\n");
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
if (tmp)
{
nv_warn("PSP did not acknowledger reset\n");
vr_warn(dev, "PSP did not acknowledger reset\n");
ret = -EINVAL;
goto out;
}
nv_info("mode1 reset succeeded\n");
vr_info(dev, "mode1 reset succeeded\n");
pci_restore_state(dev->pdev);
@@ -236,7 +221,7 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
break;
udelay(1);
}
nv_info("memsize: %x\n", tmp);
vr_info(dev, "memsize: %x\n", tmp);
/*
* this takes a long time :(
@@ -247,7 +232,7 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
break;
nv_info("PSP bootloader flags? %x, timeout: %s\n",
vr_info(dev, "PSP bootloader flags? %x, timeout: %s\n",
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no");
msleep(100);
@@ -255,11 +240,11 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L))
{
nv_warn("timed out waiting for PSP bootloader to respond after reset\n");
vr_warn(dev, "timed out waiting for PSP bootloader to respond after reset\n");
ret = -ETIME;
}
else
nv_info("PSP mode1 reset successful\n");
vr_info(dev, "PSP mode1 reset successful\n");
pci_restore_state(dev->pdev);

4
src/amd/polaris10.c
View File

@@ -17,6 +17,8 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "vendor-reset-dev.h"
#include <linux/delay.h>
#include "bif/bif_4_1_d.h"
@@ -32,7 +34,7 @@ static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
{
u32 i;
dev_info(adev->dev, "GPU pci config reset\n");
vr_info(adev->vdev, "GPU pci config reset\n");
/* reset */
pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);

32
src/amd/vega10.c
View File

@@ -18,6 +18,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/delay.h>
#include "soc15.h"
#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
@@ -38,11 +39,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#define smnMP1_FIRMWARE_FLAGS 0x3010028
static const char *log_prefix = "vega10";
#define nv_info(fmt, arg...) pci_info(dev->pdev, "%s: " fmt, log_prefix, ##arg)
#define nv_warn(fmt, arg...) pci_warn(dev->pdev, "%s: " fmt, log_prefix, ##arg)
#define nv_err(fmt, arg...) pci_err(dev->pdev, "%s: " fmt, log_prefix, ##arg)
extern int vega10_reg_base_init(struct amd_fake_dev *adev);
extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
@@ -149,7 +145,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
if (!amdgpu_get_bios(adev))
{
nv_err("amdgpu_get_bios failed: %d\n", ret);
vr_err(dev, "amdgpu_get_bios failed: %d\n", ret);
ret = -ENOTSUPP;
goto free_adev;
}
@@ -157,7 +153,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
ret = atom_bios_init(adev);
if (ret)
{
nv_err("atom_bios_init failed: %d\n", ret);
vr_err(dev, "atom_bios_init failed: %d\n", ret);
goto free_adev;
}
@@ -170,7 +166,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
udelay(1);
}
pci_info(dev->pdev, "Vega10: bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
vr_info(dev, "bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
/* collect some info for logging for now */
smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
@@ -180,16 +176,16 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L);
smu9_baco_get_state(adev, &baco_state);
pci_info(
dev->pdev,
"Vega10: SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s, baco? %s\n",
vr_info(
dev,
"SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s, baco? %s\n",
smu_resp, sol, mp1_intr ? "yes" : "no",
psp_bl_ready ? "yes" : "no",
baco_state == BACO_STATE_IN ? "on" : "off");
if (sol == ~1L && baco_state != BACO_STATE_IN)
{
pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
vr_warn(dev, "timed out waiting for SOL to be valid\n");
ret = -EINVAL;
goto free_adev;
}
@@ -202,7 +198,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
ret = smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_GetEnabledSmuFeatures, 0, &features_mask);
if (ret)
{
nv_warn("Could not get enabled SMU features, trying BACO reset anyway [ret %d]\n", ret);
vr_warn(dev, "could not get enabled SMU features, trying BACO reset anyway [ret %d]\n", ret);
goto baco_reset;
}
@@ -233,7 +229,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
* using the above sequence as ordering for the bits remaining.
*/
nv_info("Disabling features\n");
vr_info(dev, "disabling features\n");
if (features_mask & 0x00800000)
smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DisableSmuFeatures, 0x00800000, NULL);
if (features_mask & 0x00010000)
@@ -256,10 +252,10 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DisableSmuFeatures, 0x00080000, NULL);
/* driver reset */
nv_info("Driver reset\n");
vr_info(dev, "Driver reset\n");
ret = smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_GfxDeviceDriverReset, 0x2, NULL);
if (ret)
nv_warn("Could not reset w/ PPSMC_MSG_GfxDeviceDriverReset: %d\n", ret);
vr_warn(dev, "Could not reset w/ PPSMC_MSG_GfxDeviceDriverReset: %d\n", ret);
/* no reference for this, observed timing appears to be ~500ms */
msleep(500);
@@ -267,13 +263,13 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
baco_reset:
if (baco_state == BACO_STATE_OUT)
{
pci_info(dev->pdev, "Vega10: Entering BACO\n");
vr_info(dev, "entering BACO\n");
ret = vega10_baco_set_state(adev, BACO_STATE_IN);
if (ret)
return ret;
}
pci_info(dev->pdev, "Vega10: Exiting BACO\n");
vr_info(dev, "exiting BACO\n");
ret = vega10_baco_set_state(adev, BACO_STATE_OUT);
free_adev:

18
src/amd/vega20.c
View File

@@ -96,7 +96,7 @@ static int amd_vega20_mode1_reset(struct amd_fake_dev *adev)
ret = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
if (ret)
{
pci_warn(adev->pdev, "vega20: psp not working for mode1 reset\n");
vr_warn(adev->vdev, "psp not working for mode1 reset\n");
return ret;
}
@@ -107,11 +107,11 @@ static int amd_vega20_mode1_reset(struct amd_fake_dev *adev)
if (ret)
{
pci_warn(adev->pdev, "vega20: psp mode1 reset failed\n");
vr_warn(adev->vdev, "psp mode1 reset failed\n");
return ret;
}
pci_info(adev->pdev, "vega20: psp mode1 reset succeeded\n");
vr_info(adev->vdev, "psp mode1 reset succeeded\n");
return ret;
}
@@ -144,7 +144,7 @@ static int amd_vega20_reset(struct vendor_reset_dev *dev)
vega20_baco_get_state(adev, &baco_state);
if (sol == ~1L && baco_state != BACO_STATE_IN)
{
pci_warn(dev->pdev, "vega20: Timed out waiting for SOL to be valid\n");
vr_warn(dev, "Timed out waiting for SOL to be valid\n");
ret = -EINVAL;
goto free_adev;
}
@@ -152,7 +152,7 @@ static int amd_vega20_reset(struct vendor_reset_dev *dev)
/* if there's no sign of life we usually can't reset */
if (!sol)
{
pci_info(dev->pdev, "vega20: no SOL, not attempting BACO reset\n");
vr_info(dev, "no SOL, not attempting BACO reset\n");
goto free_adev;
}
@@ -165,22 +165,22 @@ static int amd_vega20_reset(struct vendor_reset_dev *dev)
goto free_adev;
}
pci_info(dev->pdev, "vega20: falling back to BACO reset\n");
vr_info(dev, "falling back to BACO reset\n");
ret = vega20_baco_set_state(adev, BACO_STATE_IN);
if (ret)
{
pci_warn(dev->pdev, "vega20: enter BACO failed\n");
vr_warn(dev, "enter BACO failed\n");
goto free_adev;
}
ret = vega20_baco_set_state(adev, BACO_STATE_OUT);
if (ret)
{
pci_warn(dev->pdev, "vega20: exit BACO failed\n");
vr_warn(dev, "exit BACO failed\n");
goto free_adev;
}
pci_info(dev->pdev, "vega20: BACO reset successful\n");
vr_info(dev, "BACO reset successful\n");
free_adev:
amd_fake_dev_fini(adev);