mirror of
https://github.com/gnif/vendor-reset.git
synced 2026-03-29 14:42:43 +02:00
Add structure for common pre- and post-reset tasks
This commit is contained in:
Adam Madsen
5
src/amd/Makefile
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5
src/amd/Makefile
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@@ -0,0 +1,5 @@
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vendor-reset-y += \
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src/amd/common.o \
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src/amd/vega10.o \
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src/amd/vega20.o \
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src/amd/navi10.o
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46
src/amd/common.c
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46
src/amd/common.c
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@@ -0,0 +1,46 @@
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include "vendor-reset-dev.h"
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#include "common.h"
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int amd_common_pre_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv;
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struct pci_dev *pdev = dev->pdev;
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priv = kzalloc(sizeof *priv, GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev->vendor_private = priv;
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spin_lock_init(&priv->pcie_lock);
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pci_set_power_state(pdev, PCI_D0);
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pci_clear_master(pdev);
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pci_save_state(pdev);
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priv->saved_state = pci_store_saved_state(pdev);
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pci_read_config_word(pdev, PCI_COMMAND, &priv->cfg);
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pci_write_config_word(pdev, PCI_COMMAND, priv->cfg | PCI_COMMAND_MEMORY | PCI_COMMAND_INTX_DISABLE);
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return 0;
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}
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int amd_common_post_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct pci_dev *pdev = dev->pdev;
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if (priv->saved_state)
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{
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pci_load_and_free_saved_state(pdev, &priv->saved_state);
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pci_restore_state(pdev);
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}
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pci_write_config_word(pdev, PCI_COMMAND, priv->cfg);
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/* don't try to go to low power if reset failed */
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if (!dev->reset_ret)
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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87
src/amd/common.h
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87
src/amd/common.h
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@@ -0,0 +1,87 @@
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/*
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Vendor Reset - Vendor Specific Reset
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Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any later
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version.
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This program is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __VENDOR_RESET_COMMON_H__
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#define __VENDOR_RESET_COMMON_H__
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#include "vendor-reset-dev.h"
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#define RREG32(reg) \
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({ \
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u32 out; \
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if ((reg) < mmio_size) \
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out = readl(mmio + (reg)); \
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else \
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{ \
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writel((reg), mmio + mmMM_INDEX); \
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out = readl(mmio + mmMM_DATA); \
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} \
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out; \
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})
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#define WREG32(reg, v) \
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do \
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{ \
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if ((reg) < mmio_size) \
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writel(v, mmio + (reg)); \
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else \
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{ \
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writel((reg), mmio + mmMM_INDEX); \
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writel(v, mmio + mmMM_DATA); \
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} \
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} while (0)
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#define WREG32_PCIE(reg, v) \
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do \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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WREG32(mmPCIE_DATA2, v); \
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(void)RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&pcie_lock, __flags); \
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} while (0)
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#define RREG32_PCIE(reg) \
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({ \
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unsigned long __flags; \
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u32 __tmp_read; \
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spin_lock_irqsave(&pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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__tmp_read = RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&pcie_lock, __flags); \
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__tmp_read; \
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})
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struct amd_vendor_private
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{
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u16 cfg;
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struct pci_saved_state *saved_state;
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spinlock_t pcie_lock;
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};
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#define amd_private(vdev) ((struct amd_vendor_private *)(vdev->vendor_private))
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int amd_common_pre_reset(struct vendor_reset_dev *);
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int amd_common_post_reset(struct vendor_reset_dev *);
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#endif
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@@ -18,7 +18,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "vendor-reset-dev.h"
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static int amd_navi10_reset(struct pci_dev * dev)
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static int amd_navi10_reset(struct vendor_reset_dev *dev)
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{
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return 0;
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}
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135
src/amd/soc15_common.h
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135
src/amd/soc15_common.h
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@@ -0,0 +1,135 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SOC15_COMMON_H__
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#define __SOC15_COMMON_H__
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/* Register Access Macros */
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#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define WREG32_FIELD15(ip, idx, reg, field, val) \
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WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
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(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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#define RREG32_SOC15(ip, inst, reg) \
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RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
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RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
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RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
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#define WREG32_SOC15(ip, inst, reg, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
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WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
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#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
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({ int ret = 0; \
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do { \
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uint32_t old_ = 0; \
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uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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uint32_t loop = adev->usec_timeout; \
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ret = 0; \
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while ((tmp_ & (mask)) != (expected_value)) { \
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if (old_ != tmp_) { \
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loop = adev->usec_timeout; \
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old_ = tmp_; \
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} else \
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udelay(1); \
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tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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loop--; \
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if (!loop) { \
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DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
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inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
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ret = -ETIMEDOUT; \
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break; \
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} \
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} \
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} while (0); \
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ret; \
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})
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#define WREG32_RLC(reg, value) \
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do { \
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if (amdgpu_sriov_fullaccess(adev)) { \
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uint32_t i = 0; \
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uint32_t retries = 50000; \
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uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \
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uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \
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uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \
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WREG32(r0, value); \
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WREG32(r1, (reg | 0x80000000)); \
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WREG32(spare_int, 0x1); \
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for (i = 0; i < retries; i++) { \
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u32 tmp = RREG32(r1); \
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if (!(tmp & 0x80000000)) \
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break; \
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udelay(10); \
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} \
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if (i >= retries) \
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pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \
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} else { \
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WREG32(reg, value); \
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} \
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} while (0)
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#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
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do { \
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uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
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if (amdgpu_sriov_fullaccess(adev)) { \
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uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \
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uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \
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uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \
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uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \
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if (target_reg == grbm_cntl) \
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WREG32(r2, value); \
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else if (target_reg == grbm_idx) \
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WREG32(r3, value); \
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WREG32(target_reg, value); \
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} else { \
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WREG32(target_reg, value); \
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} \
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} while (0)
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#define WREG32_SOC15_RLC(ip, inst, reg, value) \
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do { \
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uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
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WREG32_RLC(target_reg, value); \
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} while (0)
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#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
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WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
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(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
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WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
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#endif
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@@ -16,14 +16,18 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "soc15_common.h"
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#include "vendor-reset-dev.h"
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#include "common.h"
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static int amd_vega10_reset(struct pci_dev * dev)
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static int amd_vega10_reset(struct vendor_reset_dev *dev)
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{
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return 0;
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return 0;
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}
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const struct vendor_reset_ops amd_vega10_ops =
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{
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.reset = amd_vega10_reset
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const struct vendor_reset_ops amd_vega10_ops = {
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.pre_reset = amd_common_pre_reset,
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.reset = amd_vega10_reset,
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.post_reset = amd_common_post_reset,
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};
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@@ -18,7 +18,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "vendor-reset-dev.h"
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static int amd_vega20_reset(struct pci_dev * dev)
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static int amd_vega20_reset(struct vendor_reset_dev *dev)
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{
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return 0;
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}
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