Makussu/vendor-reset
1
0
Fork 0
mirror of https://github.com/gnif/vendor-reset.git synced 2026-03-28 13:12:43 +01:00
Code Issues Projects Releases Wiki Activity

Implement BACO for vega10.

Browse Source 
Additionally, imported a whole bunch of stuff from the `amdgpu` module.
This commit is contained in:
Adam Madsen
2020-11-01 18:48:10 -06:00
parent 1a32bb50ba
commit b8517880ea
282 changed files with 1823305 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

181
src/amd/common.h
View File

@@ -1,6 +1,7 @@
/*
Vendor Reset - Vendor Specific Reset
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free Software
@@ -19,69 +20,167 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#ifndef __VENDOR_RESET_COMMON_H__
#define __VENDOR_RESET_COMMON_H__
#include <linux/kernel.h>
#include "vendor-reset-dev.h"
#define RREG32(reg) \
({ \
u32 out; \
if ((reg) < mmio_size) \
out = readl(mmio + (reg)); \
else \
{ \
writel((reg), mmio + mmMM_INDEX); \
out = readl(mmio + mmMM_DATA); \
} \
out; \
/* from amdgpu_discovery.c */
#ifndef mmMM_INDEX
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define HW_ID_MAX 300
#endif
/* end from amdgpu_discovery.c */
#define RREG32(reg) \
({ \
u32 __out; \
if ((reg) < adev->private->mmio_size) \
__out = readl(adev->private->mmio + (reg)); \
else \
{ \
unsigned long __flags; \
spin_lock_irqsave(&adev->private->reg_lock, __flags); \
writel((reg), adev->private->mmio + mmMM_INDEX); \
__out = readl(adev->private->mmio + mmMM_DATA); \
spin_unlock_irqrestore(&adev->private->reg_lock, __flags); \
} \
__out; \
})
#define WREG32(reg, v) \
do \
{ \
if ((reg) < mmio_size) \
writel(v, mmio + (reg)); \
else \
{ \
writel((reg), mmio + mmMM_INDEX); \
writel(v, mmio + mmMM_DATA); \
} \
#define WREG32(reg, v) \
do \
{ \
if ((reg) < adev->private->mmio_size) \
writel(v, adev->private->mmio + (reg)); \
else \
{ \
unsigned long __flags; \
spin_lock_irqsave(&adev->private->reg_lock, __flags); \
writel((reg), adev->private->mmio + mmMM_INDEX); \
writel(v, adev->private->mmio + mmMM_DATA); \
spin_unlock_irqrestore(&adev->private->reg_lock, __flags); \
} \
} while (0)
#define WREG32_PCIE(reg, v) \
do \
{ \
unsigned long __flags; \
spin_lock_irqsave(&pcie_lock, __flags); \
WREG32(mmPCIE_INDEX2, reg); \
(void)RREG32(mmPCIE_INDEX2); \
WREG32(mmPCIE_DATA2, v); \
(void)RREG32(mmPCIE_DATA2); \
spin_unlock_irqrestore(&pcie_lock, __flags); \
#define WREG32_PCIE(reg, v) \
do \
{ \
unsigned long __flags; \
spin_lock_irqsave(&adev->private->pcie_lock, __flags); \
WREG32(mmPCIE_INDEX2, reg); \
(void)RREG32(mmPCIE_INDEX2); \
WREG32(mmPCIE_DATA2, v); \
(void)RREG32(mmPCIE_DATA2); \
spin_unlock_irqrestore(&adev->private->pcie_lock, __flags); \
} while (0)
#define RREG32_PCIE(reg) \
({ \
unsigned long __flags; \
u32 __tmp_read; \
spin_lock_irqsave(&pcie_lock, __flags); \
WREG32(mmPCIE_INDEX2, reg); \
(void)RREG32(mmPCIE_INDEX2); \
__tmp_read = RREG32(mmPCIE_DATA2); \
spin_unlock_irqrestore(&pcie_lock, __flags); \
__tmp_read; \
#define RREG32_PCIE(reg) \
({ \
unsigned long __flags; \
u32 __tmp_read; \
spin_lock_irqsave(&adev->private->pcie_lock, __flags); \
WREG32(mmPCIE_INDEX2, reg); \
(void)RREG32(mmPCIE_INDEX2); \
__tmp_read = RREG32(mmPCIE_DATA2); \
spin_unlock_irqrestore(&adev->private->pcie_lock, __flags); \
__tmp_read; \
})
/* from smu_cm.c */
/*
* Although these are defined in each ASIC's specific header file.
* They share the same definitions and values. That makes common
* APIs for SMC messages issuing for all ASICs possible.
*/
#define mmMP1_SMN_C2PMSG_66 0x0282
#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_82 0x0292
#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_90 0x029a
#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
/* end from smu_cm.c */
/* from amdgpu.h */
enum amd_hw_ip_block_type
{
GC_HWIP = 1,
HDP_HWIP,
SDMA0_HWIP,
SDMA1_HWIP,
SDMA2_HWIP,
SDMA3_HWIP,
SDMA4_HWIP,
SDMA5_HWIP,
SDMA6_HWIP,
SDMA7_HWIP,
MMHUB_HWIP,
ATHUB_HWIP,
NBIO_HWIP,
MP0_HWIP,
MP1_HWIP,
UVD_HWIP,
VCN_HWIP = UVD_HWIP,
JPEG_HWIP = VCN_HWIP,
VCE_HWIP,
DF_HWIP,
DCE_HWIP,
OSSSYS_HWIP,
SMUIO_HWIP,
PWR_HWIP,
NBIF_HWIP,
THM_HWIP,
CLK_HWIP,
UMC_HWIP,
RSMU_HWIP,
MAX_HWIP
};
#define HWIP_MAX_INSTANCE 8
/* end from amdgpu.h */
/* from hwmgr.h */
enum BACO_STATE
{
BACO_STATE_OUT = 0,
BACO_STATE_IN,
};
/* end from hwmgr.h */
struct amd_fake_dev
{
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
struct device *dev;
struct amd_vendor_private *private;
};
struct amd_vendor_private
{
u16 cfg;
struct pci_saved_state *saved_state;
struct amd_fake_dev adev;
resource_size_t mmio_base;
resource_size_t mmio_size;
uint32_t __iomem *mmio;
spinlock_t pcie_lock;
spinlock_t reg_lock;
struct mutex smu_lock;
};
#define to_vendor_reset_dev(priv) container_of((void *)priv, struct vendor_reset_dev, vendor_private)
#define amd_private(vdev) ((struct amd_vendor_private *)(vdev->vendor_private))
int amd_common_pre_reset(struct vendor_reset_dev *);
int amd_common_post_reset(struct vendor_reset_dev *);
int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
#endif