mirror of
https://github.com/gnif/vendor-reset.git
synced 2025-12-27 06:19:29 +01:00
[amd] added amdgpu_discovery and initial navi10 setup code
This commit is contained in:
Geoffrey McRae
parent
26e3aca758
commit
2b21a6e3cf
@ -4,10 +4,13 @@ vendor-reset-y += \
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src/amd/vega20.o \
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src/amd/navi10.o \
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src/amd/amdgpu/common_baco.o \
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src/amd/amdgpu/vega10_reg_init.o
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src/amd/amdgpu/vega10_reg_init.o \
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src/amd/amdgpu/navi10_reg_init.o \
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src/amd/amdgpu/amdgpu_device.o \
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src/amd/amdgpu/amdgpu_discovery.o
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ccflags-y += \
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-I$(src)/src/amd \
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-I$(src)/src/amd/amdgpu \
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-I$(src)/src/amd/amdgpu/include \
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$(foreach inc,$(wildcard $(src)/src/amd/amdgpu/include/asic_reg/*/.),-I$(dir $(inc)) )
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$(foreach inc,$(wildcard $(src)/src/amd/amdgpu/include/asic_reg/*/.),-I$(dir $(inc)) )
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68
src/amd/amdgpu/amdgpu_device.c
Normal file
68
src/amd/amdgpu/amdgpu_device.c
Normal file
@ -0,0 +1,68 @@
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/module.h>
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#include "common.h"
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/*
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* VRAM access helper functions
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*/
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/**
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* amdgpu_device_vram_access - read/write a buffer in vram
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*
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* @adev: amdgpu_device pointer
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* @pos: offset of the buffer in vram
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* @buf: virtual address of the buffer in system memory
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* @size: read/write size, sizeof(@buf) must > @size
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* @write: true - write to vram, otherwise - read from vram
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*/
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void amdgpu_device_vram_access(struct amd_fake_dev *adev, loff_t pos,
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uint32_t *buf, size_t size, bool write)
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{
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// unsigned long flags;
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uint32_t hi = ~0;
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uint64_t last;
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// spin_lock_irqsave(&adev->mmio_idx_lock, flags);
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for (last = pos + size; pos < last; pos += 4) {
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uint32_t tmp = pos >> 31;
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WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
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if (tmp != hi) {
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WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
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hi = tmp;
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}
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if (write)
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WREG32_NO_KIQ(mmMM_DATA, *buf++);
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else
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*buf++ = RREG32_NO_KIQ(mmMM_DATA);
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}
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// spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
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}
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2
src/amd/amdgpu/amdgpu_device.h
Normal file
2
src/amd/amdgpu/amdgpu_device.h
Normal file
@ -0,0 +1,2 @@
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void amdgpu_device_vram_access(struct amd_fake_dev *adev, loff_t pos,
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uint32_t *buf, size_t size, bool write);
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410
src/amd/amdgpu/amdgpu_discovery.c
Normal file
410
src/amd/amdgpu/amdgpu_discovery.c
Normal file
@ -0,0 +1,410 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "common.h"
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#include "amdgpu_device.h"
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#include "amdgpu_discovery.h"
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#include "soc15_hw_ip.h"
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#include "discovery.h"
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#define mmRCC_CONFIG_MEMSIZE 0xde3
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#define mmMM_INDEX 0x0
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#define mmMM_INDEX_HI 0x6
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#define mmMM_DATA 0x1
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#define HW_ID_MAX 300
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static const char *hw_id_names[HW_ID_MAX] = {
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[MP1_HWID] = "MP1",
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[MP2_HWID] = "MP2",
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[THM_HWID] = "THM",
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[SMUIO_HWID] = "SMUIO",
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[FUSE_HWID] = "FUSE",
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[CLKA_HWID] = "CLKA",
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[PWR_HWID] = "PWR",
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[GC_HWID] = "GC",
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[UVD_HWID] = "UVD",
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[AUDIO_AZ_HWID] = "AUDIO_AZ",
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[ACP_HWID] = "ACP",
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[DCI_HWID] = "DCI",
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[DMU_HWID] = "DMU",
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[DCO_HWID] = "DCO",
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[DIO_HWID] = "DIO",
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[XDMA_HWID] = "XDMA",
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[DCEAZ_HWID] = "DCEAZ",
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[DAZ_HWID] = "DAZ",
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[SDPMUX_HWID] = "SDPMUX",
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[NTB_HWID] = "NTB",
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[IOHC_HWID] = "IOHC",
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[L2IMU_HWID] = "L2IMU",
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[VCE_HWID] = "VCE",
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[MMHUB_HWID] = "MMHUB",
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[ATHUB_HWID] = "ATHUB",
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[DBGU_NBIO_HWID] = "DBGU_NBIO",
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[DFX_HWID] = "DFX",
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[DBGU0_HWID] = "DBGU0",
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[DBGU1_HWID] = "DBGU1",
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[OSSSYS_HWID] = "OSSSYS",
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[HDP_HWID] = "HDP",
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[SDMA0_HWID] = "SDMA0",
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[SDMA1_HWID] = "SDMA1",
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[ISP_HWID] = "ISP",
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[DBGU_IO_HWID] = "DBGU_IO",
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[DF_HWID] = "DF",
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[CLKB_HWID] = "CLKB",
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[FCH_HWID] = "FCH",
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[DFX_DAP_HWID] = "DFX_DAP",
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[L1IMU_PCIE_HWID] = "L1IMU_PCIE",
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[L1IMU_NBIF_HWID] = "L1IMU_NBIF",
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[L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
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[L1IMU3_HWID] = "L1IMU3",
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[L1IMU4_HWID] = "L1IMU4",
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[L1IMU5_HWID] = "L1IMU5",
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[L1IMU6_HWID] = "L1IMU6",
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[L1IMU7_HWID] = "L1IMU7",
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[L1IMU8_HWID] = "L1IMU8",
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[L1IMU9_HWID] = "L1IMU9",
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[L1IMU10_HWID] = "L1IMU10",
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[L1IMU11_HWID] = "L1IMU11",
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[L1IMU12_HWID] = "L1IMU12",
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[L1IMU13_HWID] = "L1IMU13",
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[L1IMU14_HWID] = "L1IMU14",
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[L1IMU15_HWID] = "L1IMU15",
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[WAFLC_HWID] = "WAFLC",
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[FCH_USB_PD_HWID] = "FCH_USB_PD",
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[PCIE_HWID] = "PCIE",
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[PCS_HWID] = "PCS",
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[DDCL_HWID] = "DDCL",
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[SST_HWID] = "SST",
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[IOAGR_HWID] = "IOAGR",
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[NBIF_HWID] = "NBIF",
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[IOAPIC_HWID] = "IOAPIC",
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[SYSTEMHUB_HWID] = "SYSTEMHUB",
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[NTBCCP_HWID] = "NTBCCP",
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[UMC_HWID] = "UMC",
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[SATA_HWID] = "SATA",
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[USB_HWID] = "USB",
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[CCXSEC_HWID] = "CCXSEC",
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[XGMI_HWID] = "XGMI",
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[XGBE_HWID] = "XGBE",
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[MP0_HWID] = "MP0",
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};
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static int hw_id_map[MAX_HWIP] = {
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[GC_HWIP] = GC_HWID,
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[HDP_HWIP] = HDP_HWID,
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[SDMA0_HWIP] = SDMA0_HWID,
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[SDMA1_HWIP] = SDMA1_HWID,
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[MMHUB_HWIP] = MMHUB_HWID,
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[ATHUB_HWIP] = ATHUB_HWID,
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[NBIO_HWIP] = NBIF_HWID,
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[MP0_HWIP] = MP0_HWID,
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[MP1_HWIP] = MP1_HWID,
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[UVD_HWIP] = UVD_HWID,
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[VCE_HWIP] = VCE_HWID,
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[DF_HWIP] = DF_HWID,
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[DCE_HWIP] = DMU_HWID,
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[OSSSYS_HWIP] = OSSSYS_HWID,
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[SMUIO_HWIP] = SMUIO_HWID,
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[PWR_HWIP] = PWR_HWID,
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[NBIF_HWIP] = NBIF_HWID,
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[THM_HWIP] = THM_HWID,
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[CLK_HWIP] = CLKA_HWID,
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};
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static int amdgpu_discovery_read_binary(struct amd_fake_dev *adev, uint8_t *binary)
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{
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uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
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uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
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amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
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adev->mman.discovery_tmr_size, false);
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return 0;
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}
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static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
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{
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uint16_t checksum = 0;
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int i;
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for (i = 0; i < size; i++)
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checksum += data[i];
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return checksum;
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}
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static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
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uint16_t expected)
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{
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return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
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}
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static int amdgpu_discovery_init(struct amd_fake_dev *adev)
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{
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struct table_info *info;
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struct binary_header *bhdr;
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struct ip_discovery_header *ihdr;
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struct gpu_info_header *ghdr;
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uint16_t offset;
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uint16_t size;
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uint16_t checksum;
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int r;
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adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
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adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
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if (!adev->mman.discovery_bin)
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return -ENOMEM;
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r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
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if (r) {
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DRM_ERROR("failed to read ip discovery binary\n");
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goto out;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
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DRM_ERROR("invalid ip discovery binary signature\n");
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r = -EINVAL;
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goto out;
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}
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offset = offsetof(struct binary_header, binary_checksum) +
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sizeof(bhdr->binary_checksum);
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size = bhdr->binary_size - offset;
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checksum = bhdr->binary_checksum;
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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size, checksum)) {
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DRM_ERROR("invalid ip discovery binary checksum\n");
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r = -EINVAL;
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goto out;
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}
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info = &bhdr->table_list[IP_DISCOVERY];
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offset = le16_to_cpu(info->offset);
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checksum = le16_to_cpu(info->checksum);
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ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
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if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
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DRM_ERROR("invalid ip discovery data table signature\n");
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r = -EINVAL;
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goto out;
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}
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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ihdr->size, checksum)) {
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DRM_ERROR("invalid ip discovery data table checksum\n");
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r = -EINVAL;
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goto out;
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}
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info = &bhdr->table_list[GC];
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offset = le16_to_cpu(info->offset);
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checksum = le16_to_cpu(info->checksum);
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ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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ghdr->size, checksum)) {
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DRM_ERROR("invalid gc data table checksum\n");
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r = -EINVAL;
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goto out;
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}
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return 0;
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out:
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kfree(adev->mman.discovery_bin);
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adev->mman.discovery_bin = NULL;
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return r;
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}
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void amdgpu_discovery_fini(struct amd_fake_dev *adev)
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{
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kfree(adev->mman.discovery_bin);
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adev->mman.discovery_bin = NULL;
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}
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int amdgpu_discovery_reg_base_init(struct amd_fake_dev *adev)
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{
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struct binary_header *bhdr;
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struct ip_discovery_header *ihdr;
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struct die_header *dhdr;
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struct ip *ip;
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uint16_t die_offset;
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uint16_t ip_offset;
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uint16_t num_dies;
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uint16_t num_ips;
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uint8_t num_base_address;
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int hw_ip;
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int i, j, k;
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int r;
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r = amdgpu_discovery_init(adev);
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if (r) {
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DRM_ERROR("amdgpu_discovery_init failed\n");
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return r;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
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num_dies = le16_to_cpu(ihdr->num_dies);
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DRM_DEBUG("number of dies: %d\n", num_dies);
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for (i = 0; i < num_dies; i++) {
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die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
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dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
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num_ips = le16_to_cpu(dhdr->num_ips);
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ip_offset = die_offset + sizeof(*dhdr);
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if (le16_to_cpu(dhdr->die_id) != i) {
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DRM_ERROR("invalid die id %d, expected %d\n",
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le16_to_cpu(dhdr->die_id), i);
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return -EINVAL;
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}
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DRM_DEBUG("number of hardware IPs on die%d: %d\n",
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le16_to_cpu(dhdr->die_id), num_ips);
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for (j = 0; j < num_ips; j++) {
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ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
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num_base_address = ip->num_base_address;
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DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
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hw_id_names[le16_to_cpu(ip->hw_id)],
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le16_to_cpu(ip->hw_id),
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ip->number_instance,
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ip->major, ip->minor,
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ip->revision);
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for (k = 0; k < num_base_address; k++) {
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/*
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* convert the endianness of base addresses in place,
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* so that we don't need to convert them when accessing adev->reg_offset.
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*/
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ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
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DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
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}
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for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
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if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
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DRM_DEBUG("set register base offset for %s\n",
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hw_id_names[le16_to_cpu(ip->hw_id)]);
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adev->reg_offset[hw_ip][ip->number_instance] =
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||||
ip->base_address;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int amdgpu_discovery_get_ip_version(struct amd_fake_dev *adev, int hw_id,
|
||||
int *major, int *minor, int *revision)
|
||||
{
|
||||
struct binary_header *bhdr;
|
||||
struct ip_discovery_header *ihdr;
|
||||
struct die_header *dhdr;
|
||||
struct ip *ip;
|
||||
uint16_t die_offset;
|
||||
uint16_t ip_offset;
|
||||
uint16_t num_dies;
|
||||
uint16_t num_ips;
|
||||
int i, j;
|
||||
|
||||
if (!adev->mman.discovery_bin) {
|
||||
DRM_ERROR("ip discovery uninitialized\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bhdr = (struct binary_header *)adev->mman.discovery_bin;
|
||||
ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
|
||||
le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
|
||||
num_dies = le16_to_cpu(ihdr->num_dies);
|
||||
|
||||
for (i = 0; i < num_dies; i++) {
|
||||
die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
|
||||
dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
|
||||
num_ips = le16_to_cpu(dhdr->num_ips);
|
||||
ip_offset = die_offset + sizeof(*dhdr);
|
||||
|
||||
for (j = 0; j < num_ips; j++) {
|
||||
ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
|
||||
|
||||
if (le16_to_cpu(ip->hw_id) == hw_id) {
|
||||
if (major)
|
||||
*major = ip->major;
|
||||
if (minor)
|
||||
*minor = ip->minor;
|
||||
if (revision)
|
||||
*revision = ip->revision;
|
||||
return 0;
|
||||
}
|
||||
ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int amdgpu_discovery_get_gfx_info(struct amd_fake_dev *adev)
|
||||
{
|
||||
struct binary_header *bhdr;
|
||||
struct gc_info_v1_0 *gc_info;
|
||||
|
||||
if (!adev->mman.discovery_bin) {
|
||||
DRM_ERROR("ip discovery uninitialized\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bhdr = (struct binary_header *)adev->mman.discovery_bin;
|
||||
gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
|
||||
le16_to_cpu(bhdr->table_list[GC].offset));
|
||||
|
||||
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
|
||||
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
|
||||
le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
|
||||
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
|
||||
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
|
||||
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
|
||||
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
|
||||
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
|
||||
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
|
||||
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
|
||||
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
|
||||
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
|
||||
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
|
||||
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
|
||||
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
|
||||
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
|
||||
le32_to_cpu(gc_info->gc_num_sa_per_se);
|
||||
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
38
src/amd/amdgpu/amdgpu_discovery.h
Normal file
38
src/amd/amdgpu/amdgpu_discovery.h
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_DISCOVERY__
|
||||
#define __AMDGPU_DISCOVERY__
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define DISCOVERY_TMR_SIZE (4 << 10)
|
||||
#define DISCOVERY_TMR_OFFSET (64 << 10)
|
||||
|
||||
void amdgpu_discovery_fini(struct amd_fake_dev *adev);
|
||||
int amdgpu_discovery_reg_base_init(struct amd_fake_dev *adev);
|
||||
int amdgpu_discovery_get_ip_version(struct amd_fake_dev *adev, int hw_id,
|
||||
int *major, int *minor, int *revision);
|
||||
int amdgpu_discovery_get_gfx_info(struct amd_fake_dev *adev);
|
||||
|
||||
#endif /* __AMDGPU_DISCOVERY__ */
|
||||
116
src/amd/amdgpu/amdgpu_gfx.h
Normal file
116
src/amd/amdgpu/amdgpu_gfx.h
Normal file
@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_GFX_H__
|
||||
#define __AMDGPU_GFX_H__
|
||||
|
||||
/*
|
||||
* GFX configurations
|
||||
*/
|
||||
#define AMDGPU_GFX_MAX_SE 4
|
||||
#define AMDGPU_GFX_MAX_SH_PER_SE 2
|
||||
|
||||
struct amdgpu_rb_config {
|
||||
uint32_t rb_backend_disable;
|
||||
uint32_t user_rb_backend_disable;
|
||||
uint32_t raster_config;
|
||||
uint32_t raster_config_1;
|
||||
};
|
||||
|
||||
struct gb_addr_config {
|
||||
uint16_t pipe_interleave_size;
|
||||
uint8_t num_pipes;
|
||||
uint8_t max_compress_frags;
|
||||
uint8_t num_banks;
|
||||
uint8_t num_se;
|
||||
uint8_t num_rb_per_se;
|
||||
uint8_t num_pkrs;
|
||||
};
|
||||
|
||||
struct amdgpu_gfx_config {
|
||||
unsigned max_shader_engines;
|
||||
unsigned max_tile_pipes;
|
||||
unsigned max_cu_per_sh;
|
||||
unsigned max_sh_per_se;
|
||||
unsigned max_backends_per_se;
|
||||
unsigned max_texture_channel_caches;
|
||||
unsigned max_gprs;
|
||||
unsigned max_gs_threads;
|
||||
unsigned max_hw_contexts;
|
||||
unsigned sc_prim_fifo_size_frontend;
|
||||
unsigned sc_prim_fifo_size_backend;
|
||||
unsigned sc_hiz_tile_fifo_size;
|
||||
unsigned sc_earlyz_tile_fifo_size;
|
||||
|
||||
unsigned num_tile_pipes;
|
||||
unsigned backend_enable_mask;
|
||||
unsigned mem_max_burst_length_bytes;
|
||||
unsigned mem_row_size_in_kb;
|
||||
unsigned shader_engine_tile_size;
|
||||
unsigned num_gpus;
|
||||
unsigned multi_gpu_tile_size;
|
||||
unsigned mc_arb_ramcfg;
|
||||
unsigned num_banks;
|
||||
unsigned num_ranks;
|
||||
unsigned gb_addr_config;
|
||||
unsigned num_rbs;
|
||||
unsigned gs_vgt_table_depth;
|
||||
unsigned gs_prim_buffer_depth;
|
||||
|
||||
uint32_t tile_mode_array[32];
|
||||
uint32_t macrotile_mode_array[16];
|
||||
|
||||
struct gb_addr_config gb_addr_config_fields;
|
||||
struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
|
||||
|
||||
/* gfx configure feature */
|
||||
uint32_t double_offchip_lds_buf;
|
||||
/* cached value of DB_DEBUG2 */
|
||||
uint32_t db_debug2;
|
||||
/* gfx10 specific config */
|
||||
uint32_t num_sc_per_sh;
|
||||
uint32_t num_packer_per_sc;
|
||||
uint32_t pa_sc_tile_steering_override;
|
||||
uint64_t tcc_disabled_mask;
|
||||
};
|
||||
|
||||
struct amdgpu_cu_info {
|
||||
uint32_t simd_per_cu;
|
||||
uint32_t max_waves_per_simd;
|
||||
uint32_t wave_front_size;
|
||||
uint32_t max_scratch_slots_per_cu;
|
||||
uint32_t lds_size;
|
||||
|
||||
/* total active CU number */
|
||||
uint32_t number;
|
||||
uint32_t ao_cu_mask;
|
||||
uint32_t ao_cu_bitmap[4][4];
|
||||
uint32_t bitmap[4][4];
|
||||
};
|
||||
|
||||
struct amdgpu_gfx {
|
||||
struct amdgpu_gfx_config config;
|
||||
struct amdgpu_cu_info cu_info;
|
||||
};
|
||||
|
||||
#endif
|
||||
34
src/amd/amdgpu/amdgpu_ttm.h
Normal file
34
src/amd/amdgpu/amdgpu_ttm.h
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_TTM_H__
|
||||
#define __AMDGPU_TTM_H__
|
||||
|
||||
struct amdgpu_mman {
|
||||
/* discovery */
|
||||
uint8_t *discovery_bin;
|
||||
uint32_t discovery_tmr_size;
|
||||
struct amdgpu_bo *discovery_memory;
|
||||
};
|
||||
|
||||
#endif
|
||||
164
src/amd/amdgpu/include/discovery.h
Normal file
164
src/amd/amdgpu/include/discovery.h
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DISCOVERY_H_
|
||||
#define _DISCOVERY_H_
|
||||
|
||||
#define PSP_HEADER_SIZE 256
|
||||
#define BINARY_SIGNATURE 0x28211407
|
||||
#define DISCOVERY_TABLE_SIGNATURE 0x53445049
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IP_DISCOVERY = 0,
|
||||
GC,
|
||||
HARVEST_INFO,
|
||||
TABLE_4,
|
||||
RESERVED_1,
|
||||
RESERVED_2,
|
||||
TOTAL_TABLES = 6
|
||||
} table;
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct table_info
|
||||
{
|
||||
uint16_t offset; /* Byte offset */
|
||||
uint16_t checksum; /* Byte sum of the table */
|
||||
uint16_t size; /* Table size */
|
||||
uint16_t padding;
|
||||
} table_info;
|
||||
|
||||
typedef struct binary_header
|
||||
{
|
||||
/* psp structure should go at the top of this structure */
|
||||
uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
|
||||
uint16_t version_major;
|
||||
uint16_t version_minor;
|
||||
uint16_t binary_checksum; /* Byte sum of the binary after this field */
|
||||
uint16_t binary_size; /* Binary Size*/
|
||||
table_info table_list[TOTAL_TABLES];
|
||||
} binary_header;
|
||||
|
||||
typedef struct die_info
|
||||
{
|
||||
uint16_t die_id;
|
||||
uint16_t die_offset; /* Points to the corresponding die_header structure */
|
||||
} die_info;
|
||||
|
||||
|
||||
typedef struct ip_discovery_header
|
||||
{
|
||||
uint32_t signature; /* Table Signature */
|
||||
uint16_t version; /* Table Version */
|
||||
uint16_t size; /* Table Size */
|
||||
uint32_t id; /* Table ID */
|
||||
uint16_t num_dies; /* Number of Dies */
|
||||
die_info die_info[16]; /* list die information for up to 16 dies */
|
||||
uint16_t padding[1]; /* padding */
|
||||
} ip_discovery_header;
|
||||
|
||||
typedef struct ip
|
||||
{
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t number_instance; /* instance of the IP */
|
||||
uint8_t num_base_address; /* Number of Base Addresses */
|
||||
uint8_t major; /* HCID Major */
|
||||
uint8_t minor; /* HCID Minor */
|
||||
uint8_t revision; /* HCID Revision */
|
||||
#if defined(__BIG_ENDIAN)
|
||||
uint8_t reserved : 4; /* Placeholder field */
|
||||
uint8_t harvest : 4; /* Harvest */
|
||||
#else
|
||||
uint8_t harvest : 4; /* Harvest */
|
||||
uint8_t reserved : 4; /* Placeholder field */
|
||||
#endif
|
||||
uint32_t base_address[1]; /* variable number of Addresses */
|
||||
} ip;
|
||||
|
||||
typedef struct die_header
|
||||
{
|
||||
uint16_t die_id;
|
||||
uint16_t num_ips;
|
||||
} die_header;
|
||||
|
||||
typedef struct ip_structure
|
||||
{
|
||||
ip_discovery_header* header;
|
||||
struct die
|
||||
{
|
||||
die_header *die_header;
|
||||
ip *ip_list;
|
||||
} die;
|
||||
} ip_structure;
|
||||
|
||||
struct gpu_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct gc_info_v1_0 {
|
||||
struct gpu_info_header header;
|
||||
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_wgp0_per_sa;
|
||||
uint32_t gc_num_wgp1_per_sa;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_gl2c;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_sa_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
uint32_t gc_num_gl2a;
|
||||
};
|
||||
|
||||
typedef struct harvest_info_header {
|
||||
uint32_t signature; /* Table Signature */
|
||||
uint32_t version; /* Table Version */
|
||||
} harvest_info_header;
|
||||
|
||||
typedef struct harvest_info {
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t number_instance; /* Instance of the IP */
|
||||
uint8_t reserved; /* Reserved for alignment */
|
||||
} harvest_info;
|
||||
|
||||
typedef struct harvest_table {
|
||||
harvest_info_header header;
|
||||
harvest_info list[32];
|
||||
} harvest_table;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
855
src/amd/amdgpu/include/navi10_ip_offset.h
Normal file
855
src/amd/amdgpu/include/navi10_ip_offset.h
Normal file
@ -0,0 +1,855 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _navi10_ip_offset_HEADER
|
||||
#define _navi10_ip_offset_HEADER
|
||||
|
||||
#define MAX_INSTANCE 6
|
||||
#define MAX_SEGMENT 6
|
||||
|
||||
|
||||
struct IP_BASE_INSTANCE {
|
||||
unsigned int segment[MAX_SEGMENT];
|
||||
};
|
||||
|
||||
struct IP_BASE {
|
||||
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
|
||||
};
|
||||
|
||||
|
||||
static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
|
||||
|
||||
#define ATHUB_BASE__INST0_SEG0 0x00000C00
|
||||
#define ATHUB_BASE__INST0_SEG1 0
|
||||
#define ATHUB_BASE__INST0_SEG2 0
|
||||
#define ATHUB_BASE__INST0_SEG3 0
|
||||
#define ATHUB_BASE__INST0_SEG4 0
|
||||
#define ATHUB_BASE__INST0_SEG5 0
|
||||
|
||||
#define ATHUB_BASE__INST1_SEG0 0
|
||||
#define ATHUB_BASE__INST1_SEG1 0
|
||||
#define ATHUB_BASE__INST1_SEG2 0
|
||||
#define ATHUB_BASE__INST1_SEG3 0
|
||||
#define ATHUB_BASE__INST1_SEG4 0
|
||||
#define ATHUB_BASE__INST1_SEG5 0
|
||||
|
||||
#define ATHUB_BASE__INST2_SEG0 0
|
||||
#define ATHUB_BASE__INST2_SEG1 0
|
||||
#define ATHUB_BASE__INST2_SEG2 0
|
||||
#define ATHUB_BASE__INST2_SEG3 0
|
||||
#define ATHUB_BASE__INST2_SEG4 0
|
||||
#define ATHUB_BASE__INST2_SEG5 0
|
||||
|
||||
#define ATHUB_BASE__INST3_SEG0 0
|
||||
#define ATHUB_BASE__INST3_SEG1 0
|
||||
#define ATHUB_BASE__INST3_SEG2 0
|
||||
#define ATHUB_BASE__INST3_SEG3 0
|
||||
#define ATHUB_BASE__INST3_SEG4 0
|
||||
#define ATHUB_BASE__INST3_SEG5 0
|
||||
|
||||
#define ATHUB_BASE__INST4_SEG0 0
|
||||
#define ATHUB_BASE__INST4_SEG1 0
|
||||
#define ATHUB_BASE__INST4_SEG2 0
|
||||
#define ATHUB_BASE__INST4_SEG3 0
|
||||
#define ATHUB_BASE__INST4_SEG4 0
|
||||
#define ATHUB_BASE__INST4_SEG5 0
|
||||
|
||||
#define ATHUB_BASE__INST5_SEG0 0
|
||||
#define ATHUB_BASE__INST5_SEG1 0
|
||||
#define ATHUB_BASE__INST5_SEG2 0
|
||||
#define ATHUB_BASE__INST5_SEG3 0
|
||||
#define ATHUB_BASE__INST5_SEG4 0
|
||||
#define ATHUB_BASE__INST5_SEG5 0
|
||||
|
||||
#define CLK_BASE__INST0_SEG0 0x00016C00
|
||||
#define CLK_BASE__INST0_SEG1 0x00016E00
|
||||
#define CLK_BASE__INST0_SEG2 0x00017000
|
||||
#define CLK_BASE__INST0_SEG3 0x00017200
|
||||
#define CLK_BASE__INST0_SEG4 0x00017E00
|
||||
#define CLK_BASE__INST0_SEG5 0x0001B000
|
||||
|
||||
#define CLK_BASE__INST1_SEG0 0
|
||||
#define CLK_BASE__INST1_SEG1 0
|
||||
#define CLK_BASE__INST1_SEG2 0
|
||||
#define CLK_BASE__INST1_SEG3 0
|
||||
#define CLK_BASE__INST1_SEG4 0
|
||||
#define CLK_BASE__INST1_SEG5 0
|
||||
|
||||
#define CLK_BASE__INST2_SEG0 0
|
||||
#define CLK_BASE__INST2_SEG1 0
|
||||
#define CLK_BASE__INST2_SEG2 0
|
||||
#define CLK_BASE__INST2_SEG3 0
|
||||
#define CLK_BASE__INST2_SEG4 0
|
||||
#define CLK_BASE__INST2_SEG5 0
|
||||
|
||||
#define CLK_BASE__INST3_SEG0 0
|
||||
#define CLK_BASE__INST3_SEG1 0
|
||||
#define CLK_BASE__INST3_SEG2 0
|
||||
#define CLK_BASE__INST3_SEG3 0
|
||||
#define CLK_BASE__INST3_SEG4 0
|
||||
#define CLK_BASE__INST3_SEG5 0
|
||||
|
||||
#define CLK_BASE__INST4_SEG0 0
|
||||
#define CLK_BASE__INST4_SEG1 0
|
||||
#define CLK_BASE__INST4_SEG2 0
|
||||
#define CLK_BASE__INST4_SEG3 0
|
||||
#define CLK_BASE__INST4_SEG4 0
|
||||
#define CLK_BASE__INST4_SEG5 0
|
||||
|
||||
#define CLK_BASE__INST5_SEG0 0
|
||||
#define CLK_BASE__INST5_SEG1 0
|
||||
#define CLK_BASE__INST5_SEG2 0
|
||||
#define CLK_BASE__INST5_SEG3 0
|
||||
#define CLK_BASE__INST5_SEG4 0
|
||||
#define CLK_BASE__INST5_SEG5 0
|
||||
|
||||
#define DF_BASE__INST0_SEG0 0x00007000
|
||||
#define DF_BASE__INST0_SEG1 0
|
||||
#define DF_BASE__INST0_SEG2 0
|
||||
#define DF_BASE__INST0_SEG3 0
|
||||
#define DF_BASE__INST0_SEG4 0
|
||||
#define DF_BASE__INST0_SEG5 0
|
||||
|
||||
#define DF_BASE__INST1_SEG0 0
|
||||
#define DF_BASE__INST1_SEG1 0
|
||||
#define DF_BASE__INST1_SEG2 0
|
||||
#define DF_BASE__INST1_SEG3 0
|
||||
#define DF_BASE__INST1_SEG4 0
|
||||
#define DF_BASE__INST1_SEG5 0
|
||||
|
||||
#define DF_BASE__INST2_SEG0 0
|
||||
#define DF_BASE__INST2_SEG1 0
|
||||
#define DF_BASE__INST2_SEG2 0
|
||||
#define DF_BASE__INST2_SEG3 0
|
||||
#define DF_BASE__INST2_SEG4 0
|
||||
#define DF_BASE__INST2_SEG5 0
|
||||
|
||||
#define DF_BASE__INST3_SEG0 0
|
||||
#define DF_BASE__INST3_SEG1 0
|
||||
#define DF_BASE__INST3_SEG2 0
|
||||
#define DF_BASE__INST3_SEG3 0
|
||||
#define DF_BASE__INST3_SEG4 0
|
||||
#define DF_BASE__INST3_SEG5 0
|
||||
|
||||
#define DF_BASE__INST4_SEG0 0
|
||||
#define DF_BASE__INST4_SEG1 0
|
||||
#define DF_BASE__INST4_SEG2 0
|
||||
#define DF_BASE__INST4_SEG3 0
|
||||
#define DF_BASE__INST4_SEG4 0
|
||||
#define DF_BASE__INST4_SEG5 0
|
||||
|
||||
#define DF_BASE__INST5_SEG0 0
|
||||
#define DF_BASE__INST5_SEG1 0
|
||||
#define DF_BASE__INST5_SEG2 0
|
||||
#define DF_BASE__INST5_SEG3 0
|
||||
#define DF_BASE__INST5_SEG4 0
|
||||
#define DF_BASE__INST5_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST0_SEG0 0x00000012
|
||||
#define DCN_BASE__INST0_SEG1 0x000000C0
|
||||
#define DCN_BASE__INST0_SEG2 0x000034C0
|
||||
#define DCN_BASE__INST0_SEG3 0x00009000
|
||||
#define DCN_BASE__INST0_SEG4 0
|
||||
#define DCN_BASE__INST0_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST1_SEG0 0
|
||||
#define DCN_BASE__INST1_SEG1 0
|
||||
#define DCN_BASE__INST1_SEG2 0
|
||||
#define DCN_BASE__INST1_SEG3 0
|
||||
#define DCN_BASE__INST1_SEG4 0
|
||||
#define DCN_BASE__INST1_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST2_SEG0 0
|
||||
#define DCN_BASE__INST2_SEG1 0
|
||||
#define DCN_BASE__INST2_SEG2 0
|
||||
#define DCN_BASE__INST2_SEG3 0
|
||||
#define DCN_BASE__INST2_SEG4 0
|
||||
#define DCN_BASE__INST2_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST3_SEG0 0
|
||||
#define DCN_BASE__INST3_SEG1 0
|
||||
#define DCN_BASE__INST3_SEG2 0
|
||||
#define DCN_BASE__INST3_SEG3 0
|
||||
#define DCN_BASE__INST3_SEG4 0
|
||||
#define DCN_BASE__INST3_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST4_SEG0 0
|
||||
#define DCN_BASE__INST4_SEG1 0
|
||||
#define DCN_BASE__INST4_SEG2 0
|
||||
#define DCN_BASE__INST4_SEG3 0
|
||||
#define DCN_BASE__INST4_SEG4 0
|
||||
#define DCN_BASE__INST4_SEG5 0
|
||||
|
||||
#define DCN_BASE__INST5_SEG0 0
|
||||
#define DCN_BASE__INST5_SEG1 0
|
||||
#define DCN_BASE__INST5_SEG2 0
|
||||
#define DCN_BASE__INST5_SEG3 0
|
||||
#define DCN_BASE__INST5_SEG4 0
|
||||
#define DCN_BASE__INST5_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST0_SEG0 0x00017400
|
||||
#define FUSE_BASE__INST0_SEG1 0
|
||||
#define FUSE_BASE__INST0_SEG2 0
|
||||
#define FUSE_BASE__INST0_SEG3 0
|
||||
#define FUSE_BASE__INST0_SEG4 0
|
||||
#define FUSE_BASE__INST0_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST1_SEG0 0
|
||||
#define FUSE_BASE__INST1_SEG1 0
|
||||
#define FUSE_BASE__INST1_SEG2 0
|
||||
#define FUSE_BASE__INST1_SEG3 0
|
||||
#define FUSE_BASE__INST1_SEG4 0
|
||||
#define FUSE_BASE__INST1_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST2_SEG0 0
|
||||
#define FUSE_BASE__INST2_SEG1 0
|
||||
#define FUSE_BASE__INST2_SEG2 0
|
||||
#define FUSE_BASE__INST2_SEG3 0
|
||||
#define FUSE_BASE__INST2_SEG4 0
|
||||
#define FUSE_BASE__INST2_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST3_SEG0 0
|
||||
#define FUSE_BASE__INST3_SEG1 0
|
||||
#define FUSE_BASE__INST3_SEG2 0
|
||||
#define FUSE_BASE__INST3_SEG3 0
|
||||
#define FUSE_BASE__INST3_SEG4 0
|
||||
#define FUSE_BASE__INST3_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST4_SEG0 0
|
||||
#define FUSE_BASE__INST4_SEG1 0
|
||||
#define FUSE_BASE__INST4_SEG2 0
|
||||
#define FUSE_BASE__INST4_SEG3 0
|
||||
#define FUSE_BASE__INST4_SEG4 0
|
||||
#define FUSE_BASE__INST4_SEG5 0
|
||||
|
||||
#define FUSE_BASE__INST5_SEG0 0
|
||||
#define FUSE_BASE__INST5_SEG1 0
|
||||
#define FUSE_BASE__INST5_SEG2 0
|
||||
#define FUSE_BASE__INST5_SEG3 0
|
||||
#define FUSE_BASE__INST5_SEG4 0
|
||||
#define FUSE_BASE__INST5_SEG5 0
|
||||
|
||||
#define GC_BASE__INST0_SEG0 0x00001260
|
||||
#define GC_BASE__INST0_SEG1 0x0000A000
|
||||
#define GC_BASE__INST0_SEG2 0
|
||||
#define GC_BASE__INST0_SEG3 0
|
||||
#define GC_BASE__INST0_SEG4 0
|
||||
#define GC_BASE__INST0_SEG5 0
|
||||
|
||||
#define GC_BASE__INST1_SEG0 0
|
||||
#define GC_BASE__INST1_SEG1 0
|
||||
#define GC_BASE__INST1_SEG2 0
|
||||
#define GC_BASE__INST1_SEG3 0
|
||||
#define GC_BASE__INST1_SEG4 0
|
||||
#define GC_BASE__INST1_SEG5 0
|
||||
|
||||
#define GC_BASE__INST2_SEG0 0
|
||||
#define GC_BASE__INST2_SEG1 0
|
||||
#define GC_BASE__INST2_SEG2 0
|
||||
#define GC_BASE__INST2_SEG3 0
|
||||
#define GC_BASE__INST2_SEG4 0
|
||||
#define GC_BASE__INST2_SEG5 0
|
||||
|
||||
#define GC_BASE__INST3_SEG0 0
|
||||
#define GC_BASE__INST3_SEG1 0
|
||||
#define GC_BASE__INST3_SEG2 0
|
||||
#define GC_BASE__INST3_SEG3 0
|
||||
#define GC_BASE__INST3_SEG4 0
|
||||
#define GC_BASE__INST3_SEG5 0
|
||||
|
||||
#define GC_BASE__INST4_SEG0 0
|
||||
#define GC_BASE__INST4_SEG1 0
|
||||
#define GC_BASE__INST4_SEG2 0
|
||||
#define GC_BASE__INST4_SEG3 0
|
||||
#define GC_BASE__INST4_SEG4 0
|
||||
#define GC_BASE__INST4_SEG5 0
|
||||
|
||||
#define GC_BASE__INST5_SEG0 0
|
||||
#define GC_BASE__INST5_SEG1 0
|
||||
#define GC_BASE__INST5_SEG2 0
|
||||
#define GC_BASE__INST5_SEG3 0
|
||||
#define GC_BASE__INST5_SEG4 0
|
||||
#define GC_BASE__INST5_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST0_SEG0 0x00000F20
|
||||
#define HDP_BASE__INST0_SEG1 0
|
||||
#define HDP_BASE__INST0_SEG2 0
|
||||
#define HDP_BASE__INST0_SEG3 0
|
||||
#define HDP_BASE__INST0_SEG4 0
|
||||
#define HDP_BASE__INST0_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST1_SEG0 0
|
||||
#define HDP_BASE__INST1_SEG1 0
|
||||
#define HDP_BASE__INST1_SEG2 0
|
||||
#define HDP_BASE__INST1_SEG3 0
|
||||
#define HDP_BASE__INST1_SEG4 0
|
||||
#define HDP_BASE__INST1_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST2_SEG0 0
|
||||
#define HDP_BASE__INST2_SEG1 0
|
||||
#define HDP_BASE__INST2_SEG2 0
|
||||
#define HDP_BASE__INST2_SEG3 0
|
||||
#define HDP_BASE__INST2_SEG4 0
|
||||
#define HDP_BASE__INST2_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST3_SEG0 0
|
||||
#define HDP_BASE__INST3_SEG1 0
|
||||
#define HDP_BASE__INST3_SEG2 0
|
||||
#define HDP_BASE__INST3_SEG3 0
|
||||
#define HDP_BASE__INST3_SEG4 0
|
||||
#define HDP_BASE__INST3_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST4_SEG0 0
|
||||
#define HDP_BASE__INST4_SEG1 0
|
||||
#define HDP_BASE__INST4_SEG2 0
|
||||
#define HDP_BASE__INST4_SEG3 0
|
||||
#define HDP_BASE__INST4_SEG4 0
|
||||
#define HDP_BASE__INST4_SEG5 0
|
||||
|
||||
#define HDP_BASE__INST5_SEG0 0
|
||||
#define HDP_BASE__INST5_SEG1 0
|
||||
#define HDP_BASE__INST5_SEG2 0
|
||||
#define HDP_BASE__INST5_SEG3 0
|
||||
#define HDP_BASE__INST5_SEG4 0
|
||||
#define HDP_BASE__INST5_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST0_SEG0 0x0001A000
|
||||
#define MMHUB_BASE__INST0_SEG1 0
|
||||
#define MMHUB_BASE__INST0_SEG2 0
|
||||
#define MMHUB_BASE__INST0_SEG3 0
|
||||
#define MMHUB_BASE__INST0_SEG4 0
|
||||
#define MMHUB_BASE__INST0_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST1_SEG0 0
|
||||
#define MMHUB_BASE__INST1_SEG1 0
|
||||
#define MMHUB_BASE__INST1_SEG2 0
|
||||
#define MMHUB_BASE__INST1_SEG3 0
|
||||
#define MMHUB_BASE__INST1_SEG4 0
|
||||
#define MMHUB_BASE__INST1_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST2_SEG0 0
|
||||
#define MMHUB_BASE__INST2_SEG1 0
|
||||
#define MMHUB_BASE__INST2_SEG2 0
|
||||
#define MMHUB_BASE__INST2_SEG3 0
|
||||
#define MMHUB_BASE__INST2_SEG4 0
|
||||
#define MMHUB_BASE__INST2_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST3_SEG0 0
|
||||
#define MMHUB_BASE__INST3_SEG1 0
|
||||
#define MMHUB_BASE__INST3_SEG2 0
|
||||
#define MMHUB_BASE__INST3_SEG3 0
|
||||
#define MMHUB_BASE__INST3_SEG4 0
|
||||
#define MMHUB_BASE__INST3_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST4_SEG0 0
|
||||
#define MMHUB_BASE__INST4_SEG1 0
|
||||
#define MMHUB_BASE__INST4_SEG2 0
|
||||
#define MMHUB_BASE__INST4_SEG3 0
|
||||
#define MMHUB_BASE__INST4_SEG4 0
|
||||
#define MMHUB_BASE__INST4_SEG5 0
|
||||
|
||||
#define MMHUB_BASE__INST5_SEG0 0
|
||||
#define MMHUB_BASE__INST5_SEG1 0
|
||||
#define MMHUB_BASE__INST5_SEG2 0
|
||||
#define MMHUB_BASE__INST5_SEG3 0
|
||||
#define MMHUB_BASE__INST5_SEG4 0
|
||||
#define MMHUB_BASE__INST5_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST0_SEG0 0x00016000
|
||||
#define MP0_BASE__INST0_SEG1 0
|
||||
#define MP0_BASE__INST0_SEG2 0
|
||||
#define MP0_BASE__INST0_SEG3 0
|
||||
#define MP0_BASE__INST0_SEG4 0
|
||||
#define MP0_BASE__INST0_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST1_SEG0 0
|
||||
#define MP0_BASE__INST1_SEG1 0
|
||||
#define MP0_BASE__INST1_SEG2 0
|
||||
#define MP0_BASE__INST1_SEG3 0
|
||||
#define MP0_BASE__INST1_SEG4 0
|
||||
#define MP0_BASE__INST1_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST2_SEG0 0
|
||||
#define MP0_BASE__INST2_SEG1 0
|
||||
#define MP0_BASE__INST2_SEG2 0
|
||||
#define MP0_BASE__INST2_SEG3 0
|
||||
#define MP0_BASE__INST2_SEG4 0
|
||||
#define MP0_BASE__INST2_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST3_SEG0 0
|
||||
#define MP0_BASE__INST3_SEG1 0
|
||||
#define MP0_BASE__INST3_SEG2 0
|
||||
#define MP0_BASE__INST3_SEG3 0
|
||||
#define MP0_BASE__INST3_SEG4 0
|
||||
#define MP0_BASE__INST3_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST4_SEG0 0
|
||||
#define MP0_BASE__INST4_SEG1 0
|
||||
#define MP0_BASE__INST4_SEG2 0
|
||||
#define MP0_BASE__INST4_SEG3 0
|
||||
#define MP0_BASE__INST4_SEG4 0
|
||||
#define MP0_BASE__INST4_SEG5 0
|
||||
|
||||
#define MP0_BASE__INST5_SEG0 0
|
||||
#define MP0_BASE__INST5_SEG1 0
|
||||
#define MP0_BASE__INST5_SEG2 0
|
||||
#define MP0_BASE__INST5_SEG3 0
|
||||
#define MP0_BASE__INST5_SEG4 0
|
||||
#define MP0_BASE__INST5_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST0_SEG0 0x00016000
|
||||
#define MP1_BASE__INST0_SEG1 0
|
||||
#define MP1_BASE__INST0_SEG2 0
|
||||
#define MP1_BASE__INST0_SEG3 0
|
||||
#define MP1_BASE__INST0_SEG4 0
|
||||
#define MP1_BASE__INST0_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST1_SEG0 0
|
||||
#define MP1_BASE__INST1_SEG1 0
|
||||
#define MP1_BASE__INST1_SEG2 0
|
||||
#define MP1_BASE__INST1_SEG3 0
|
||||
#define MP1_BASE__INST1_SEG4 0
|
||||
#define MP1_BASE__INST1_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST2_SEG0 0
|
||||
#define MP1_BASE__INST2_SEG1 0
|
||||
#define MP1_BASE__INST2_SEG2 0
|
||||
#define MP1_BASE__INST2_SEG3 0
|
||||
#define MP1_BASE__INST2_SEG4 0
|
||||
#define MP1_BASE__INST2_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST3_SEG0 0
|
||||
#define MP1_BASE__INST3_SEG1 0
|
||||
#define MP1_BASE__INST3_SEG2 0
|
||||
#define MP1_BASE__INST3_SEG3 0
|
||||
#define MP1_BASE__INST3_SEG4 0
|
||||
#define MP1_BASE__INST3_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST4_SEG0 0
|
||||
#define MP1_BASE__INST4_SEG1 0
|
||||
#define MP1_BASE__INST4_SEG2 0
|
||||
#define MP1_BASE__INST4_SEG3 0
|
||||
#define MP1_BASE__INST4_SEG4 0
|
||||
#define MP1_BASE__INST4_SEG5 0
|
||||
|
||||
#define MP1_BASE__INST5_SEG0 0
|
||||
#define MP1_BASE__INST5_SEG1 0
|
||||
#define MP1_BASE__INST5_SEG2 0
|
||||
#define MP1_BASE__INST5_SEG3 0
|
||||
#define MP1_BASE__INST5_SEG4 0
|
||||
#define MP1_BASE__INST5_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST0_SEG0 0x00000000
|
||||
#define NBIO_BASE__INST0_SEG1 0x00000014
|
||||
#define NBIO_BASE__INST0_SEG2 0x00000D20
|
||||
#define NBIO_BASE__INST0_SEG3 0x00010400
|
||||
#define NBIO_BASE__INST0_SEG4 0
|
||||
#define NBIO_BASE__INST0_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST1_SEG0 0
|
||||
#define NBIO_BASE__INST1_SEG1 0
|
||||
#define NBIO_BASE__INST1_SEG2 0
|
||||
#define NBIO_BASE__INST1_SEG3 0
|
||||
#define NBIO_BASE__INST1_SEG4 0
|
||||
#define NBIO_BASE__INST1_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST2_SEG0 0
|
||||
#define NBIO_BASE__INST2_SEG1 0
|
||||
#define NBIO_BASE__INST2_SEG2 0
|
||||
#define NBIO_BASE__INST2_SEG3 0
|
||||
#define NBIO_BASE__INST2_SEG4 0
|
||||
#define NBIO_BASE__INST2_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST3_SEG0 0
|
||||
#define NBIO_BASE__INST3_SEG1 0
|
||||
#define NBIO_BASE__INST3_SEG2 0
|
||||
#define NBIO_BASE__INST3_SEG3 0
|
||||
#define NBIO_BASE__INST3_SEG4 0
|
||||
#define NBIO_BASE__INST3_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST4_SEG0 0
|
||||
#define NBIO_BASE__INST4_SEG1 0
|
||||
#define NBIO_BASE__INST4_SEG2 0
|
||||
#define NBIO_BASE__INST4_SEG3 0
|
||||
#define NBIO_BASE__INST4_SEG4 0
|
||||
#define NBIO_BASE__INST4_SEG5 0
|
||||
|
||||
#define NBIO_BASE__INST5_SEG0 0
|
||||
#define NBIO_BASE__INST5_SEG1 0
|
||||
#define NBIO_BASE__INST5_SEG2 0
|
||||
#define NBIO_BASE__INST5_SEG3 0
|
||||
#define NBIO_BASE__INST5_SEG4 0
|
||||
#define NBIO_BASE__INST5_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST0_SEG0 0x000010A0
|
||||
#define OSSSYS_BASE__INST0_SEG1 0
|
||||
#define OSSSYS_BASE__INST0_SEG2 0
|
||||
#define OSSSYS_BASE__INST0_SEG3 0
|
||||
#define OSSSYS_BASE__INST0_SEG4 0
|
||||
#define OSSSYS_BASE__INST0_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST1_SEG0 0
|
||||
#define OSSSYS_BASE__INST1_SEG1 0
|
||||
#define OSSSYS_BASE__INST1_SEG2 0
|
||||
#define OSSSYS_BASE__INST1_SEG3 0
|
||||
#define OSSSYS_BASE__INST1_SEG4 0
|
||||
#define OSSSYS_BASE__INST1_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST2_SEG0 0
|
||||
#define OSSSYS_BASE__INST2_SEG1 0
|
||||
#define OSSSYS_BASE__INST2_SEG2 0
|
||||
#define OSSSYS_BASE__INST2_SEG3 0
|
||||
#define OSSSYS_BASE__INST2_SEG4 0
|
||||
#define OSSSYS_BASE__INST2_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST3_SEG0 0
|
||||
#define OSSSYS_BASE__INST3_SEG1 0
|
||||
#define OSSSYS_BASE__INST3_SEG2 0
|
||||
#define OSSSYS_BASE__INST3_SEG3 0
|
||||
#define OSSSYS_BASE__INST3_SEG4 0
|
||||
#define OSSSYS_BASE__INST3_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST4_SEG0 0
|
||||
#define OSSSYS_BASE__INST4_SEG1 0
|
||||
#define OSSSYS_BASE__INST4_SEG2 0
|
||||
#define OSSSYS_BASE__INST4_SEG3 0
|
||||
#define OSSSYS_BASE__INST4_SEG4 0
|
||||
#define OSSSYS_BASE__INST4_SEG5 0
|
||||
|
||||
#define OSSSYS_BASE__INST5_SEG0 0
|
||||
#define OSSSYS_BASE__INST5_SEG1 0
|
||||
#define OSSSYS_BASE__INST5_SEG2 0
|
||||
#define OSSSYS_BASE__INST5_SEG3 0
|
||||
#define OSSSYS_BASE__INST5_SEG4 0
|
||||
#define OSSSYS_BASE__INST5_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST0_SEG0 0x00012000
|
||||
#define RSMU_BASE__INST0_SEG1 0
|
||||
#define RSMU_BASE__INST0_SEG2 0
|
||||
#define RSMU_BASE__INST0_SEG3 0
|
||||
#define RSMU_BASE__INST0_SEG4 0
|
||||
#define RSMU_BASE__INST0_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST1_SEG0 0
|
||||
#define RSMU_BASE__INST1_SEG1 0
|
||||
#define RSMU_BASE__INST1_SEG2 0
|
||||
#define RSMU_BASE__INST1_SEG3 0
|
||||
#define RSMU_BASE__INST1_SEG4 0
|
||||
#define RSMU_BASE__INST1_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST2_SEG0 0
|
||||
#define RSMU_BASE__INST2_SEG1 0
|
||||
#define RSMU_BASE__INST2_SEG2 0
|
||||
#define RSMU_BASE__INST2_SEG3 0
|
||||
#define RSMU_BASE__INST2_SEG4 0
|
||||
#define RSMU_BASE__INST2_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST3_SEG0 0
|
||||
#define RSMU_BASE__INST3_SEG1 0
|
||||
#define RSMU_BASE__INST3_SEG2 0
|
||||
#define RSMU_BASE__INST3_SEG3 0
|
||||
#define RSMU_BASE__INST3_SEG4 0
|
||||
#define RSMU_BASE__INST3_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST4_SEG0 0
|
||||
#define RSMU_BASE__INST4_SEG1 0
|
||||
#define RSMU_BASE__INST4_SEG2 0
|
||||
#define RSMU_BASE__INST4_SEG3 0
|
||||
#define RSMU_BASE__INST4_SEG4 0
|
||||
#define RSMU_BASE__INST4_SEG5 0
|
||||
|
||||
#define RSMU_BASE__INST5_SEG0 0
|
||||
#define RSMU_BASE__INST5_SEG1 0
|
||||
#define RSMU_BASE__INST5_SEG2 0
|
||||
#define RSMU_BASE__INST5_SEG3 0
|
||||
#define RSMU_BASE__INST5_SEG4 0
|
||||
#define RSMU_BASE__INST5_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST0_SEG0 0x00016800
|
||||
#define SMUIO_BASE__INST0_SEG1 0x00016A00
|
||||
#define SMUIO_BASE__INST0_SEG2 0
|
||||
#define SMUIO_BASE__INST0_SEG3 0
|
||||
#define SMUIO_BASE__INST0_SEG4 0
|
||||
#define SMUIO_BASE__INST0_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST1_SEG0 0
|
||||
#define SMUIO_BASE__INST1_SEG1 0
|
||||
#define SMUIO_BASE__INST1_SEG2 0
|
||||
#define SMUIO_BASE__INST1_SEG3 0
|
||||
#define SMUIO_BASE__INST1_SEG4 0
|
||||
#define SMUIO_BASE__INST1_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST2_SEG0 0
|
||||
#define SMUIO_BASE__INST2_SEG1 0
|
||||
#define SMUIO_BASE__INST2_SEG2 0
|
||||
#define SMUIO_BASE__INST2_SEG3 0
|
||||
#define SMUIO_BASE__INST2_SEG4 0
|
||||
#define SMUIO_BASE__INST2_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST3_SEG0 0
|
||||
#define SMUIO_BASE__INST3_SEG1 0
|
||||
#define SMUIO_BASE__INST3_SEG2 0
|
||||
#define SMUIO_BASE__INST3_SEG3 0
|
||||
#define SMUIO_BASE__INST3_SEG4 0
|
||||
#define SMUIO_BASE__INST3_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST4_SEG0 0
|
||||
#define SMUIO_BASE__INST4_SEG1 0
|
||||
#define SMUIO_BASE__INST4_SEG2 0
|
||||
#define SMUIO_BASE__INST4_SEG3 0
|
||||
#define SMUIO_BASE__INST4_SEG4 0
|
||||
#define SMUIO_BASE__INST4_SEG5 0
|
||||
|
||||
#define SMUIO_BASE__INST5_SEG0 0
|
||||
#define SMUIO_BASE__INST5_SEG1 0
|
||||
#define SMUIO_BASE__INST5_SEG2 0
|
||||
#define SMUIO_BASE__INST5_SEG3 0
|
||||
#define SMUIO_BASE__INST5_SEG4 0
|
||||
#define SMUIO_BASE__INST5_SEG5 0
|
||||
|
||||
#define THM_BASE__INST0_SEG0 0x00016600
|
||||
#define THM_BASE__INST0_SEG1 0
|
||||
#define THM_BASE__INST0_SEG2 0
|
||||
#define THM_BASE__INST0_SEG3 0
|
||||
#define THM_BASE__INST0_SEG4 0
|
||||
#define THM_BASE__INST0_SEG5 0
|
||||
|
||||
#define THM_BASE__INST1_SEG0 0
|
||||
#define THM_BASE__INST1_SEG1 0
|
||||
#define THM_BASE__INST1_SEG2 0
|
||||
#define THM_BASE__INST1_SEG3 0
|
||||
#define THM_BASE__INST1_SEG4 0
|
||||
#define THM_BASE__INST1_SEG5 0
|
||||
|
||||
#define THM_BASE__INST2_SEG0 0
|
||||
#define THM_BASE__INST2_SEG1 0
|
||||
#define THM_BASE__INST2_SEG2 0
|
||||
#define THM_BASE__INST2_SEG3 0
|
||||
#define THM_BASE__INST2_SEG4 0
|
||||
#define THM_BASE__INST2_SEG5 0
|
||||
|
||||
#define THM_BASE__INST3_SEG0 0
|
||||
#define THM_BASE__INST3_SEG1 0
|
||||
#define THM_BASE__INST3_SEG2 0
|
||||
#define THM_BASE__INST3_SEG3 0
|
||||
#define THM_BASE__INST3_SEG4 0
|
||||
#define THM_BASE__INST3_SEG5 0
|
||||
|
||||
#define THM_BASE__INST4_SEG0 0
|
||||
#define THM_BASE__INST4_SEG1 0
|
||||
#define THM_BASE__INST4_SEG2 0
|
||||
#define THM_BASE__INST4_SEG3 0
|
||||
#define THM_BASE__INST4_SEG4 0
|
||||
#define THM_BASE__INST4_SEG5 0
|
||||
|
||||
#define THM_BASE__INST5_SEG0 0
|
||||
#define THM_BASE__INST5_SEG1 0
|
||||
#define THM_BASE__INST5_SEG2 0
|
||||
#define THM_BASE__INST5_SEG3 0
|
||||
#define THM_BASE__INST5_SEG4 0
|
||||
#define THM_BASE__INST5_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST0_SEG0 0x00014000
|
||||
#define UMC_BASE__INST0_SEG1 0
|
||||
#define UMC_BASE__INST0_SEG2 0
|
||||
#define UMC_BASE__INST0_SEG3 0
|
||||
#define UMC_BASE__INST0_SEG4 0
|
||||
#define UMC_BASE__INST0_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST1_SEG0 0
|
||||
#define UMC_BASE__INST1_SEG1 0
|
||||
#define UMC_BASE__INST1_SEG2 0
|
||||
#define UMC_BASE__INST1_SEG3 0
|
||||
#define UMC_BASE__INST1_SEG4 0
|
||||
#define UMC_BASE__INST1_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST2_SEG0 0
|
||||
#define UMC_BASE__INST2_SEG1 0
|
||||
#define UMC_BASE__INST2_SEG2 0
|
||||
#define UMC_BASE__INST2_SEG3 0
|
||||
#define UMC_BASE__INST2_SEG4 0
|
||||
#define UMC_BASE__INST2_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST3_SEG0 0
|
||||
#define UMC_BASE__INST3_SEG1 0
|
||||
#define UMC_BASE__INST3_SEG2 0
|
||||
#define UMC_BASE__INST3_SEG3 0
|
||||
#define UMC_BASE__INST3_SEG4 0
|
||||
#define UMC_BASE__INST3_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST4_SEG0 0
|
||||
#define UMC_BASE__INST4_SEG1 0
|
||||
#define UMC_BASE__INST4_SEG2 0
|
||||
#define UMC_BASE__INST4_SEG3 0
|
||||
#define UMC_BASE__INST4_SEG4 0
|
||||
#define UMC_BASE__INST4_SEG5 0
|
||||
|
||||
#define UMC_BASE__INST5_SEG0 0
|
||||
#define UMC_BASE__INST5_SEG1 0
|
||||
#define UMC_BASE__INST5_SEG2 0
|
||||
#define UMC_BASE__INST5_SEG3 0
|
||||
#define UMC_BASE__INST5_SEG4 0
|
||||
#define UMC_BASE__INST5_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST0_SEG0 0x00007800
|
||||
#define VCN_BASE__INST0_SEG1 0x00007E00
|
||||
#define VCN_BASE__INST0_SEG2 0
|
||||
#define VCN_BASE__INST0_SEG3 0
|
||||
#define VCN_BASE__INST0_SEG4 0
|
||||
#define VCN_BASE__INST0_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST1_SEG0 0
|
||||
#define VCN_BASE__INST1_SEG1 0
|
||||
#define VCN_BASE__INST1_SEG2 0
|
||||
#define VCN_BASE__INST1_SEG3 0
|
||||
#define VCN_BASE__INST1_SEG4 0
|
||||
#define VCN_BASE__INST1_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST2_SEG0 0
|
||||
#define VCN_BASE__INST2_SEG1 0
|
||||
#define VCN_BASE__INST2_SEG2 0
|
||||
#define VCN_BASE__INST2_SEG3 0
|
||||
#define VCN_BASE__INST2_SEG4 0
|
||||
#define VCN_BASE__INST2_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST3_SEG0 0
|
||||
#define VCN_BASE__INST3_SEG1 0
|
||||
#define VCN_BASE__INST3_SEG2 0
|
||||
#define VCN_BASE__INST3_SEG3 0
|
||||
#define VCN_BASE__INST3_SEG4 0
|
||||
#define VCN_BASE__INST3_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST4_SEG0 0
|
||||
#define VCN_BASE__INST4_SEG1 0
|
||||
#define VCN_BASE__INST4_SEG2 0
|
||||
#define VCN_BASE__INST4_SEG3 0
|
||||
#define VCN_BASE__INST4_SEG4 0
|
||||
#define VCN_BASE__INST4_SEG5 0
|
||||
|
||||
#define VCN_BASE__INST5_SEG0 0
|
||||
#define VCN_BASE__INST5_SEG1 0
|
||||
#define VCN_BASE__INST5_SEG2 0
|
||||
#define VCN_BASE__INST5_SEG3 0
|
||||
#define VCN_BASE__INST5_SEG4 0
|
||||
#define VCN_BASE__INST5_SEG5 0
|
||||
|
||||
#endif
|
||||
32
src/amd/amdgpu/include/nbio_v2_3.h
Normal file
32
src/amd/amdgpu/include/nbio_v2_3.h
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NBIO_V2_3_H__
|
||||
#define __NBIO_V2_3_H__
|
||||
|
||||
#include "soc15_common.h"
|
||||
|
||||
extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;
|
||||
extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;
|
||||
|
||||
#endif
|
||||
39
src/amd/amdgpu/include/nv.h
Normal file
39
src/amd/amdgpu/include/nv.h
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NV_H__
|
||||
#define __NV_H__
|
||||
|
||||
#include "nbio_v2_3.h"
|
||||
|
||||
void nv_grbm_select(struct amd_fake_dev *adev,
|
||||
u32 me, u32 pipe, u32 queue, u32 vmid);
|
||||
void nv_set_virt_ops(struct amd_fake_dev *adev);
|
||||
int nv_set_ip_blocks(struct amd_fake_dev *adev);
|
||||
int navi10_reg_base_init(struct amd_fake_dev *adev);
|
||||
int navi14_reg_base_init(struct amd_fake_dev *adev);
|
||||
int navi12_reg_base_init(struct amd_fake_dev *adev);
|
||||
int sienna_cichlid_reg_base_init(struct amd_fake_dev *adev);
|
||||
void vangogh_reg_base_init(struct amd_fake_dev *adev);
|
||||
int dimgrey_cavefish_reg_base_init(struct amd_fake_dev *adev);
|
||||
#endif
|
||||
53
src/amd/amdgpu/navi10_reg_init.c
Normal file
53
src/amd/amdgpu/navi10_reg_init.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include "common.h"
|
||||
#include "nv.h"
|
||||
|
||||
#include "soc15_common.h"
|
||||
#include "navi10_ip_offset.h"
|
||||
|
||||
int navi10_reg_base_init(struct amd_fake_dev *adev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
|
||||
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
|
||||
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
|
||||
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
|
||||
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
|
||||
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
|
||||
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
|
||||
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
|
||||
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
|
||||
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
|
||||
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
|
||||
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
|
||||
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
|
||||
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
|
||||
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
|
||||
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
|
||||
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -88,6 +88,11 @@ Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
__tmp_read; \
|
||||
})
|
||||
|
||||
/* KIQ is only used for SRIOV accesses, we are not targetting these devices so
|
||||
* we can safely just wrap the defines */
|
||||
#define WREG32_NO_KIQ WREG32
|
||||
#define RREG32_NO_KIQ RREG32
|
||||
|
||||
/* from smu_cm.c */
|
||||
/*
|
||||
* Although these are defined in each ASIC's specific header file.
|
||||
@ -144,9 +149,16 @@ enum amd_hw_ip_block_type
|
||||
#define HWIP_MAX_INSTANCE 8
|
||||
/* end from amdgpu.h */
|
||||
|
||||
#include "amdgpu_gfx.h"
|
||||
#include "amdgpu_ttm.h"
|
||||
#include "drm/drm_print.h"
|
||||
|
||||
struct amd_fake_dev
|
||||
{
|
||||
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
||||
struct amdgpu_gfx gfx;
|
||||
struct amdgpu_mman mman;
|
||||
|
||||
struct device *dev;
|
||||
struct amd_vendor_private *private;
|
||||
};
|
||||
@ -176,4 +188,4 @@ int amd_common_post_reset(struct vendor_reset_dev *);
|
||||
int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
|
||||
int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -18,12 +18,39 @@ Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
#include "vendor-reset-dev.h"
|
||||
|
||||
#include "common.h"
|
||||
#include "amdgpu_discovery.h"
|
||||
#include "nv.h"
|
||||
|
||||
static int amd_navi10_reset(struct vendor_reset_dev *dev)
|
||||
{
|
||||
struct amd_vendor_private *priv = amd_private(dev);
|
||||
struct amd_fake_dev *adev;
|
||||
int ret;
|
||||
|
||||
priv->adev = (struct amd_fake_dev){
|
||||
.dev = &dev->pdev->dev,
|
||||
.private = priv,
|
||||
};
|
||||
adev = &priv->adev;
|
||||
|
||||
ret = amdgpu_discovery_reg_base_init(adev);
|
||||
if (ret < 0)
|
||||
{
|
||||
pci_info(dev->pdev,
|
||||
"amdgpu_discovery_reg_base_init failed, using legacy method");
|
||||
navi10_reg_base_init(adev);
|
||||
}
|
||||
|
||||
if (adev->mman.discovery_bin)
|
||||
amdgpu_discovery_fini(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct vendor_reset_ops amd_navi10_ops =
|
||||
{
|
||||
.reset = amd_navi10_reset
|
||||
.pre_reset = amd_common_pre_reset,
|
||||
.reset = amd_navi10_reset,
|
||||
.post_reset = amd_common_post_reset,
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user