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https://github.com/gnif/vendor-reset.git
synced 2026-03-28 13:12:43 +01:00
[amd] added amdgpu_discovery and initial navi10 setup code
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@@ -88,6 +88,11 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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__tmp_read; \
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})
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/* KIQ is only used for SRIOV accesses, we are not targetting these devices so
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* we can safely just wrap the defines */
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#define WREG32_NO_KIQ WREG32
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#define RREG32_NO_KIQ RREG32
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/* from smu_cm.c */
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/*
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* Although these are defined in each ASIC's specific header file.
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@@ -144,9 +149,16 @@ enum amd_hw_ip_block_type
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#define HWIP_MAX_INSTANCE 8
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/* end from amdgpu.h */
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#include "amdgpu_gfx.h"
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#include "amdgpu_ttm.h"
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#include "drm/drm_print.h"
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struct amd_fake_dev
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{
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uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
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struct amdgpu_gfx gfx;
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struct amdgpu_mman mman;
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struct device *dev;
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struct amd_vendor_private *private;
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};
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@@ -176,4 +188,4 @@ int amd_common_post_reset(struct vendor_reset_dev *);
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int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
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int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp);
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#endif
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#endif
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