mirror of
https://github.com/gnif/vendor-reset.git
synced 2025-12-26 22:09:28 +01:00
WIP: implement BACO reset for Navi10
This commit is contained in:
Adam Madsen
parent
a6458b3dbf
commit
e82aa63e2b
@ -82,7 +82,10 @@ int amd_common_pre_reset(struct vendor_reset_dev *dev)
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pci_save_state(pdev);
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priv->saved_state = pci_store_saved_state(pdev);
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pci_read_config_word(pdev, PCI_COMMAND, &priv->cfg);
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pci_write_config_word(pdev, PCI_COMMAND, priv->cfg | PCI_COMMAND_MEMORY | PCI_COMMAND_INTX_DISABLE);
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pci_write_config_word(pdev, PCI_COMMAND, priv->cfg | PCI_COMMAND_MEMORY);
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if (!pci_wait_for_pending_transaction(pdev))
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vr_warn(dev, "Timed out waiting for transaction to clear\n");
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return 0;
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@ -115,8 +118,8 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
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pci_write_config_word(pdev, PCI_COMMAND, priv->cfg);
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/* don't try to go to low power if reset failed */
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if (!dev->reset_ret)
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pci_set_power_state(pdev, PCI_D3hot);
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// if (!dev->reset_ret)
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// pci_set_power_state(pdev, PCI_D3hot);
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kfree(priv);
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dev->vendor_private = NULL;
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@ -25,4 +25,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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int atom_bios_init(struct amd_fake_dev *adev);
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void atom_bios_fini(struct amd_fake_dev *adev);
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/* this is actually in amdgpu_bios.c */
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bool amdgpu_get_bios(struct amd_fake_dev *adev);
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#endif
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305
src/amd/navi10.c
305
src/amd/navi10.c
@ -33,15 +33,149 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "nv.h"
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#include "psp_gfx_if.h"
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#include "smu_v11_0_ppsmc.h"
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#include "thm/thm_11_0_2_offset.h"
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#include "thm/thm_11_0_2_sh_mask.h"
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extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
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enum navi10_reset_type
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{
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NAVI10_RESET_NONE,
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NAVI10_RESET_BACO,
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NAVI10_RESET_MODE1,
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};
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static int navi10_needs_reset(struct vendor_reset_dev *dev, enum navi10_reset_type *type)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev = &priv->adev;
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u32 smu_resp, mp1_intr, psp_bl_ready, sol;
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/* collect some state info */
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sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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mp1_intr = (RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
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psp_bl_ready = !!(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L);
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vr_info(dev, "SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
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smu_resp, sol, mp1_intr ? "yes" : "no",
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psp_bl_ready ? "yes" : "no");
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if (sol == 0x0 && !mp1_intr && psp_bl_ready)
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/* okay, if we're in this state, we're probably reset */
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*type = NAVI10_RESET_NONE;
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else if (sol && sol != ~1L && mp1_intr && psp_bl_ready)
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*type = NAVI10_RESET_BACO;
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else
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*type = NAVI10_RESET_MODE1;
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return *type != NAVI10_RESET_NONE;
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}
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static int navi10_mode1_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev = &priv->adev;
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u32 offset, tmp;
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int ret = 0, timeout;
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vr_info(dev, "begin psp mode 1 reset\n");
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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pci_save_state(dev->pdev);
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/* check validity of PSP before reset */
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
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if (tmp)
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vr_warn(dev, "timed out waiting for PSP to reach valid state, but continuing anyway\n");
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/* reset command */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
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msleep(500);
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/* wait for ACK */
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
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if (tmp)
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{
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vr_warn(dev, "PSP did not acknowledger reset\n");
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ret = -EINVAL;
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goto out;
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}
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vr_info(dev, "mode1 reset succeeded\n");
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pci_restore_state(dev->pdev);
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for (timeout = 100000; timeout; --timeout)
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{
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tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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if (tmp != 0xffffffff)
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break;
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udelay(1);
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}
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out:
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return ret;
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}
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static int navi10_wait_for_psp_ready(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev = &priv->adev;
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int timeout;
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/*
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* this takes a long time :(
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*/
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for (timeout = 100; timeout; --timeout)
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{
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/* see if PSP bootloader comes back */
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if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
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return 0;
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msleep(100);
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}
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return (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L) ? 0 : -ETIMEDOUT;
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}
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static int navi10_baco_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev = &priv->adev;
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int ret, tmp;
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vr_info(dev, "Entering BACO\n");
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/* BACO_SEQ_BACO */
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ret = smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_ArmD3, 0, NULL);
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if (ret)
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return ret;
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tmp = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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tmp |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, tmp);
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ret = smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_EnterBaco, 0, NULL);
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if (ret)
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return ret;
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msleep(500);
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vr_info(dev, "Exiting BACO\n");
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ret = smum_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_ExitBaco, 0, NULL);
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return ret;
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}
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static int amd_navi10_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev;
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int ret = 0, timeout;
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u32 sol, smu_resp, mp1_intr, psp_bl_ready, tmp, offset;
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u32 sol;
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enum navi10_reset_type reset_type;
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adev = &priv->adev;
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ret = amd_fake_dev_init(adev, dev);
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@ -93,141 +227,37 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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}
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if (sol == ~1L)
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{
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vr_warn(dev, "Timed out waiting for SOL to be valid\n");
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/* continuing anyway because sometimes it can still be reset from here */
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}
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vr_warn(dev, "Timed out waiting for SOL to be valid\n");
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vr_info(dev, "bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
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/* collect some info for logging for now */
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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mp1_intr = (RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
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psp_bl_ready = !!(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L);
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vr_info(dev, "SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
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smu_resp, sol, mp1_intr ? "yes" : "no",
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psp_bl_ready ? "yes" : "no");
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/* okay, if we're in this state, we're probably reset */
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if (sol == 0x0 && !mp1_intr && psp_bl_ready)
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if (!navi10_needs_reset(dev, &reset_type))
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goto free_adev;
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/* this tells the drivers nvram is lost and everything needs to be reset */
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vr_info(dev, "Clearing scratch regs 6 and 7\n");
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WREG32(adev->bios_scratch_reg_offset + 6, 0);
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WREG32(adev->bios_scratch_reg_offset + 7, 0);
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/* it only makes sense to reset mp1 if it's running
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* XXX: is this even necessary? in early testing, I ran into
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* situations where MP1 was alive but not responsive, but in
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* later testing I have not been able to replicate this scenario.
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*/
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if (smu_resp != 0x01 && mp1_intr)
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{
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vr_info(dev, "MP1 reset\n");
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & MP1_SMN_PUB_CTRL__RESET_MASK);
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
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vr_info(dev, "wait for MP1\n");
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for (timeout = 100000; timeout; --timeout)
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{
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tmp = RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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if ((tmp &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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break;
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udelay(1);
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}
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if (!timeout &&
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!((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT))
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{
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vr_warn(dev, "timed out waiting for MP1 reset\n");
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}
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smu_wait(adev);
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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vr_info(dev, "SMU resp reg: %x\n", tmp);
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}
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/*
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* again, this only makes sense if we have an SMU to talk to
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* some of these may fail, that's okay. we're just turning off as many
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* things as possible
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*/
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if (mp1_intr)
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{
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smum_send_msg_to_smc(adev, PPSMC_MSG_DisallowGfxOff, NULL);
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smum_send_msg_to_smc(adev, PPSMC_MSG_PrepareMp1ForReset, NULL);
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}
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vr_info(dev, "begin psp mode 1 reset\n");
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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pci_save_state(dev->pdev);
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/* check validity of PSP before reset */
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
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if (tmp)
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vr_warn(dev, "timed out waiting for PSP to reach valid state, but continuing anyway\n");
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/* reset command */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
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msleep(500);
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/* wait for ACK */
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
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if (tmp)
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{
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vr_warn(dev, "PSP did not acknowledger reset\n");
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ret = -EINVAL;
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goto out;
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}
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vr_info(dev, "mode1 reset succeeded\n");
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pci_restore_state(dev->pdev);
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for (timeout = 100000; timeout; --timeout)
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{
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tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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if (tmp != 0xffffffff)
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break;
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udelay(1);
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}
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/*
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* this takes a long time :(
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*/
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for (timeout = 100; timeout; --timeout)
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{
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/* see if PSP bootloader comes back */
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if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
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break;
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msleep(100);
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}
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if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L))
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{
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vr_warn(dev, "timed out waiting for PSP bootloader to respond after reset\n");
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ret = -ETIME;
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}
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if (reset_type == NAVI10_RESET_MODE1)
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ret = navi10_baco_reset(dev);
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else
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vr_info(dev, "PSP mode1 reset successful\n");
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{
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ret = navi10_mode1_reset(dev);
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if (ret)
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goto mode1_out;
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out:
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pci_restore_state(dev->pdev);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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if ((ret = navi10_wait_for_psp_ready(dev)))
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vr_warn(dev, "timed out waiting for PSP bootloader to respond after reset\n");
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else
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vr_info(dev, "PSP mode1 reset successful\n");
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mode1_out:
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pci_restore_state(dev->pdev);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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}
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if (!ret)
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{
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/* this tells the drivers nvram is lost and everything needs to be reset */
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vr_info(dev, "Clearing scratch regs 6 and 7\n");
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WREG32(adev->bios_scratch_reg_offset + 6, 0);
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WREG32(adev->bios_scratch_reg_offset + 7, 0);
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}
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free_adev:
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amd_fake_dev_fini(adev);
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@ -235,11 +265,10 @@ free_adev:
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return ret;
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}
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const struct vendor_reset_ops amd_navi10_ops =
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{
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.version = {1, 1},
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.probe = amd_common_probe,
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.pre_reset = amd_common_pre_reset,
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.reset = amd_navi10_reset,
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.post_reset = amd_common_post_reset,
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const struct vendor_reset_ops amd_navi10_ops = {
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.version = {2, 0},
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.probe = amd_common_probe,
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.pre_reset = amd_common_pre_reset,
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.reset = amd_navi10_reset,
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.post_reset = amd_common_post_reset,
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};
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